本帖最后由 long9998 于 2011-7-13 16:44 编辑
module feng(clk,start,receive,ctrla0,ctrla1,ctrla2,ctrla3,ctrltri5,multia0,multia1,multia2,adclk);
input clk,start;
input receive;
output ctrla0,ctrla1,ctrla2,ctrla3,ctrltri5,multia0,multia1,multia2;
output adclk;
reg [16:0] clkreg ;
reg [1:0] trans;
reg adclk;
reg ctrla0,ctrla1,ctrla2,ctrla3,multia0,multia1,multia2,gate;
wire clko;
wire chufa;
assign chufa=clkreg[16]; //assign chufa=clkreg[20];
assign clko=clk & gate;
always @(posedge clk)
begin
adclk<=adclk+1;
end
always @(posedge start or posedge receive)
begin
if(start)
gate<=1;
else
gate<=0;
end
//always @(posedge nRes or negedge chufa)
always @( negedge chufa)
//begin
// if(nRes)
case(trans)
0: begin
ctrla0=0; //state for GB1
ctrla1=1;
ctrla2=1;
ctrla3=1;
multia0=1;
multia1=0;
multia2=0;
end
1: begin
ctrla0=1; //state for GB2
ctrla1=1;
ctrla2=0;
ctrla3=1;
multia0=0;
multia1=1;
multia2=0;
trans<=2;
end
2: begin
ctrla0=1; //state for GB3
ctrla1=1;
ctrla2=1;
ctrla3=0;
multia0=0;
multia1=0;
multia2=1;
trans<=3;
end
3: begin
ctrla0=1; //state for GB0
ctrla1=0;
ctrla2=1;
ctrla3=1;
multia0=1;
multia1=1;
multia2=0;
trans<=0;
end
default:
begin
ctrla0=0; //state for GB0
ctrla1=1;
ctrla2=1;
ctrla3=1;
trans<=0;
end
endcase
always @(posedge clk)
clkreg<=clkreg+1;
assign ctrltri5=clkreg[16];
endmodule
有这样的两条警告
@W:"E:\feng\main.v":2:10:2:14|Input start is unused
@W:"E:\feng\main.v":3:6:3:12|Input receive is unused
为什么会出现这样的警告呢？我在第二个always里用了啊
求高手解答
要是这个warning不影响后面的我也就不管了，可是有这个warning后面分配管脚都不能分配了 |
楼主
标题置顶
标题高亮
