architecture behav of nios_fifo_ram_interface is
signal nARE_delay1,nARE_delay2 :std_logic;
signal nAWE_delay1,nAWE_delay2 :std_logic;
begin
process(reset_b,clk)
begin
if reset_b = '0' then
nARE_delay1 <= '1';
nARE_delay2 <= '1';
nAWE_delay2 <= '1';
nAWE_delay1 <= '1';
elsif clk'event and clk='1' then
nARE_delay2 <= nARE_delay1;
nARE_delay1 <= nARE;
nAWE_delay2 <= nAWE_delay1;
nAWE_delay1 <= nAWE;
end if;
end process;
……
if (nAWE_delay2 ='1' and nAWE_delay1='0') then
……
请问下时钟上升沿的操作有什么用呢
下面为什么执行那样的判断呢 | 
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