`timescale 1ns / 1ps
`include "../rtl/ddr_parameters_0.v"
module ddr_infrastructure_iobs_0
(
input clk,
output [`CLK_WIDTH-1:0] ddr_ck,
output [`CLK_WIDTH-1:0] ddr_ck_n
);
wire [`CLK_WIDTH-1:0] ddr_ck_q;
wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;
//***************************************************************************
// Memory clock generation
//***************************************************************************
genvar clk_i;
generate
for (clk_i = 0; clk_i < `CLK_WIDTH; clk_i = clk_i+1) begin : gen_clk
ODDR #
(
.SRTYPE ("SYNC"),
.DDR_CLK_EDGE ("OPPOSITE_EDGE")
)
oddr_clk
(
.Q(ddr_ck_q[clk_i]),
.C(clk),
.CE(vcc),
.D1(gnd),
.D2(vcc),
.R(gnd),
.S(gnd)
);
OBUFDS obufds_clk
(
.I(ddr_ck_q[clk_i]),
.O(ddr_ck[clk_i]),
.OB(ddr_ck_n[clk_i])
);
end
endgenerate
endmodule
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