这是代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; --输入预加和地址码产生
entity Address is
port( a0,a1,a2,a3,a4,a5,a6,a7: in std_logic_vector(7 downto 0);--输入寄存器
a8,a9,a10,a11,a12,a13,a14,a15: in std_logic_vector(7 downto 0);--输入寄存器
clk :in std_logic;--输入时钟
y0,y1,y2,y3,y4,y5,y6,y7,y8:out std_logic_vector(7 downto 0));--地址输出
end Address;
architecture arc of Address is
signal b0,b1,b2,b3,b4,b5,b6,b7:std_logic_vector(8 downto 0);
begin
b0<=(a0(0)&a0)+(a8(0)&a8);
b1<=(a1(0)&a1)+(a9(0)&a9);
b2<=(a2(0)&a2)+(a10(0)&a10);
b3<=(a3(0)&a3)+(a11(0)&a11);
b4<=(a4(0)&a4)+(a12(0)&a12);
b5<=(a5(0)&a5)+(a13(0)&a13);
b6<=(a6(0)&a6)+(a14(0)&a14);
b7<=(a7(0)&a7)+(a15(0)&a15);
process(clk)
begin if clk'event and clk='1'then--下面产生的8位位矢量将作为LUT的地址
y0<=b7(0)&b6(0)&b5(0)&b4(0)&b3(0)&b2(0)&b1(0)&b0(0);
y1<=b7(1)&b6(1)&b5(1)&b4(1)&b3(1)&b2(1)&b1(1)&b0(1);
y2<=b7(2)&b6(2)&b5(2)&b4(2)&b3(2)&b2(2)&b1(2)&b0(2);
y3<=b7(3)&b6(3)&b5(3)&b4(3)&b3(3)&b2(3)&b1(3)&b0(3);
y4<=b7(4)&b6(4)&b5(4)&b4(4)&b3(4)&b2(4)&b1(4)&b0(4);
y5<=b7(5)&b6(5)&b5(5)&b4(5)&b3(5)&b2(5)&b1(5)&b0(5);
y6<=b7(6)&b6(6)&b5(6)&b4(6)&b3(6)&b2(6)&b1(6)&b0(6);
y7<=b7(7)&b6(7)&b5(7)&b4(7)&b3(7)&b2(7)&b1(7)&b0(7);
y8<=b7(8)&b6(8)&b5(8)&b4(8)&b3(8)&b2(8)&b1(8)&b0(8);
end if;
end process; end arc；
|
楼主
标题置顶
标题高亮
