One TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
40 GMAC/20 GFLOP @ 1.2GHz
32KB L1P, 32KB L1D, 512KB L2
1 MB Shared L2
Multicore Navigator and TeraNet Switch Fabric - 2 Tb
Network Coprocessors- Packet Accelerator, Security Accelerator
Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
HyperLink - 50Gbaud Operation, Full Duplex
Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
UART Interface
I2C Interface
16 GPIO Pins
SPI Interface
Sixteen 64-Bit Timers
Three On-Chip PLLsv |
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