程序求大神注释

只看该作者 · 2018-5-24 10:59

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY keys_lock IS
PORT (
clk ,clr,status  : IN STD_LOGIC ;
   selout : OUT  STD_LOGIC_VECTOR (2 downto 0) ;
key    : IN STD_LOGIC_VECTOR (3 downto 0) ;
segout : OUT STD_LOGIC_VECTOR (0  TO 6);
locks,unlocks: OUT STD_LOGIC
      );
END keys_lock ;

ARCHITECTURE doit of keys_lock IS
signal counter1 : std_logic_vector(1 downto 0);
signal counter : std_logic_vector(2 downto 0);
signal counter2 : std_logic_vector(4 downto 0);
signal dc0,dc1,dc2,dc3,lock0,lock1,lock2,lock3 : std_logic_vector(3 downto 0);
signal dcc1 : std_logic_vector(4 downto 0);
signal dcc : std_logic_vector(6 downto 0);
signal d0,d1,d2,d3 : std_logic_vector(0 to 6);
signal clk1,test,koff: std_logic;
component decode
  PORT(
ssin : in  std_logic_vector(3 downto 0);
ssout: out std_logic_vector(0 to 6)
);
end component;
begin

test<=key(3) and key(2) and key(1) and key(0);

P1: process(clr,clk)
begin
if(clr='0') then
   counter1<="00";
elsif(clk'event and clk='1') then
   counter1<=counter1+1;
end if;
end process P1;

clk1<='0' when counter1<="01" else
   '1';

P2: process(clr,clk1,test)
begin
if(clr='0') then
   counter<="000";
elsif(clk1'event and clk1='1') then
   if(test='0') or (koff='0') then
   counter<=counter;
   else
   counter<=counter+1;
   end if;
end if;
end process P2;

selout<=counter;
dcc<=counter & key;

P3: process(clk,test)
begin
if(clk'event and clk='0') then
   if(dcc="0001110") then
      dcc1<="00000";
   elsif(dcc="0011110") then
      dcc1<="00001";
   elsif(dcc="0101110") then
      dcc1<="00010";
   elsif(dcc="0111110") then
      dcc1<="00011";
   elsif(dcc="1101110") then
      dcc1<="00100";
   elsif(dcc="1111110") then
      dcc1<="00101";
   elsif(dcc="0001101") then
      dcc1<="00110";
   elsif(dcc="0011101") then
      dcc1<="00111";
   elsif(dcc="1001101") then
      dcc1<="01000";
   elsif(dcc="1011101") then
      dcc1<="01001";
   elsif(dcc="1101101") then
      dcc1<="01010";
   elsif(dcc="1111101") then
      dcc1<="01011";
   elsif(dcc="0101011") then
      dcc1<="01100";
   elsif(dcc="0111011") then
      dcc1<="01101";
   elsif(dcc="1001011") then
      dcc1<="01110";
   elsif(dcc="1011011") then
      dcc1<="01111";
   elsif(dcc="1001110") then
      dcc1<="10000";
   elsif(dcc="1011110") then
      dcc1<="10001";
   elsif(test='0') then
      dcc1<="01111";
   end if;
end if;
end process P3;

--dcc1<="0000" when (dcc="0001110") else
--    "0001" when (dcc="0011110") else
--    "0010" when (dcc="0101110") else
--    "0011" when (dcc="0111110") else
--    "0100" when (dcc="1101110") else
--    "0101" when (dcc="1111110") else
--    "0110" when (dcc="0001101") else
--    "0111" when (dcc="0011101") else
--    "1000" when (dcc="1001101") else
--    "1001" when (dcc="1011101") else
--    "1010" when (dcc="1101101") else
--    "1011" when (dcc="1111101") else
--    "1100" when (dcc="0101011") else
--    "1101" when (dcc="0111011") else
--    "1110" when (dcc="1001011") else
--    "1111" when (dcc="1011011") else
--    "0000";

P4: process(test,clk,clr)
begin
if(clr='0') then
   counter2<="00000";
   koff<='1';
elsif(clk'event and clk='1') then
   if(test='0') then
      counter2<="00000";
      koff<='0';
   elsif(counter2<"11110") then
      counter2<=counter2+1;
-- end if;
   elsif(counter2="11110") then
   koff<='1';
   end if;
end if;
end process P4;
--koff<='0' when counter2<="01110"  else
--    '1';

P5: process(koff,clr)
begin
if(clr='0') then
   dc0<="0000";
   dc1<="0000";
   dc2<="0000";
   dc3<="0000";
   locks<='0';
   unlocks<='0';
elsif(koff'event and koff='1') then
if(dcc1="10000" and status='0') then
   lock0<=dc0;
   lock1<=dc1;
   lock2<=dc2;
   lock3<=dc3;
   locks<='1';
   unlocks<='0';
elsif(dcc1="10001" and status='1') then
   if(dc0=lock0 and dc1=lock1 and dc2=lock2 and dc3=lock3) then
      locks<='0';
      unlocks<='1';
   end if;
else
   dc0<=dcc1(3 downto 0);
   dc1<=dc0;
   dc2<=dc1;
   dc3<=dc2;
end if;
  end if;
end process P5;

U1: decode port map(ssin=>dc0, ssout=>d0);
U2: decode port map(ssin=>dc1, ssout=>d1);
U3: decode port map(ssin=>dc2, ssout=>d2);
U4: decode port map(ssin=>dc3, ssout=>d3);

segout<=d0 when counter="000" else
      d1 when counter="001" else
      d2 when counter="010" else
      d3 when counter="011" else
      "0000000";

end doit;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY decode IS
PORT(
  ssin : in  std_logic_vector(3 downto 0);
  ssout: out std_logic_vector(0 to 6)
);
end decode;

ARCHITECTURE a of decode IS
begin
  ssout<="1111110" when ssin="0000" else
      "0110000" when ssin="0001" else
      "1101101" when ssin="0010" else
      "1111001" when ssin="0011" else
      "0110011" when ssin="0100" else
      "1011011" when ssin="0101" else
      "1011111" when ssin="0110" else
      "1110000" when ssin="0111" else
      "1111111" when ssin="1000" else
      "1111011" when ssin="1001" else
      "1110111" when ssin="1010" else
      "0011111" when ssin="1011" else
      "1001110" when ssin="1100" else
      "0111101" when ssin="1101" else
      "1001111" when ssin="1110" else
      "1000111" when ssin="1111" else
   "0000000";
end a;