关于新版IAR for STM8 的问题,怎么解决

只看该作者 · 2018-5-24 16:50

举个列子：
__no_init volatile unsigned char PA_ODR @0x5000;
__no_init volatile unsigned char PA_ODR1 @0x5000;

// 指向同一个地址要报错，老版本的IAR 就不会有这个问题

Error[Lp025]: absolute section .near.noinit (main.o #11) ([0x005000-0x005000]) overlaps with absolute section .near.noinit (main.o #9) ([0x005000-0x005000])

只看该作者 · 2018-5-24 18:03

法克，你重叠位置了。

只看该作者 · 2018-5-24 18:04

这个版本不许定义重叠的变量。

只看该作者 · 2018-5-24 19:09

本帖最后由大王123 于 2018-5-24 19:10 编辑

xinpian101 发表于 2018-5-24 18:04
这个版本不许定义重叠的变量。

我两个地方都要用到啊
typedef struct
{
unsigned char B0: 1;
unsigned char B1: 1;
unsigned char B2: 1;
unsigned char B3: 1;
unsigned char B4: 1;
unsigned char B5: 1;
unsigned char B6: 1;
unsigned char B7: 1;

}  SBitChar;

typedef  struct
{
      SBitChar  ODR;
      SBitChar  IDR;
      SBitChar  DDR;
      SBitChar  CR1;
      SBitChar  CR2;

}  GPIO;

__no_init volatile GPIO PA @ 0x5000;
__no_init volatile GPIO PB @ 0x5005;
__no_init volatile GPIO PC @ 0x500A;
__no_init volatile GPIO PD @ 0x500F;
__no_init volatile GPIO PE @ 0x5014;
__no_init volatile GPIO PF @ 0x5019;
__no_init volatile GPIO PG @ 0x501E;
__no_init volatile GPIO PI @ 0x5028;

----------------------------------------------------------------------------------------------------------------------------------------#define DEF_8BIT_REG_AT(NAME,ADDRESS) __no_init  volatile  unsigned char NAME @ADDRESS
#define DEF_16BIT_REG_AT(NAME,ADDRESS)  __no_init  volatile  unsigned int  NAME @ADDRESS

/* Port A data output latch register */
DEF_8BIT_REG_AT(PA_ODR,0x5000);

/* Port A input pin value register */
DEF_8BIT_REG_AT(PA_IDR,0x5001);

/* Port A data direction register */
DEF_8BIT_REG_AT(PA_DDR,0x5002);

/* Port A control register 1 */
DEF_8BIT_REG_AT(PA_CR1,0x5003);

/* Port A control register 2 */
DEF_8BIT_REG_AT(PA_CR2,0x5004);

/* Port B */
/*****************************************************************/

/* Port B data output latch register */
DEF_8BIT_REG_AT(PB_ODR,0x5005);

/* Port B input pin value register */
DEF_8BIT_REG_AT(PB_IDR,0x5006);

/* Port B data direction register */
DEF_8BIT_REG_AT(PB_DDR,0x5007);

/* Port B control register 1 */
DEF_8BIT_REG_AT(PB_CR1,0x5008);

/* Port B control register 2 */
DEF_8BIT_REG_AT(PB_CR2,0x5009);

/* Port C */
/*****************************************************************/

/* Port C data output latch register */
DEF_8BIT_REG_AT(PC_ODR,0x500a);

/* Port C input pin value register */
DEF_8BIT_REG_AT(PC_IDR,0x500b);

/* Port C data direction register */
DEF_8BIT_REG_AT(PC_DDR,0x500c);

/* Port C control register 1 */
DEF_8BIT_REG_AT(PC_CR1,0x500d);

/* Port C control register 2 */
DEF_8BIT_REG_AT(PC_CR2,0x500e);