请教ISE综合时序不满足时的报告解读

只看该作者 · 2011-8-2 14:55

Phase  5  : 0 unrouted; (Setup:22, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 22 secs

Phase  6  : 0 unrouted; (Setup:22, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 22 secs

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 34 secs

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 34 secs

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 34 secs

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:6472)    REAL time: 1 mins 34 secs

经常遇到的都是setup达不到0，这里却是Component Switching Limit，这是什么意思呢？一般是指哪里出问题了才会有这样的报告出来呢？

只看该作者 · 2011-8-2 14:58

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "ap_clk" 2 ns HIGH 50%;

33402 paths analyzed, 4912 endpoints analyzed, 0 failing endpoints
8 timing errors detected. (0 setup errors, 0 hold errors, 8 component switching limit errors)
Minimum period is 2.809ns.
--------------------------------------------------------------------------------
这是.twr里面的，看关键路径好像没问题
  Requirement:       2.000ns
  Data Path Delay:    1.955ns (Levels of Logic = 5)
  Clock Path Skew:    0.000ns
  Source Clock:       ap_clk rising at 0.000ns
  Destination Clock: ap_clk rising at 2.000ns
  Clock Uncertainty: 0.035ns

只看该作者 · 2011-8-2 15:02

难道是指这些DSP跑不到500MHz？

Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "ap_clk" 2 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -0.809ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 2.809ns (355.999MHz) (Tdspper_AREG_PREG_MULT)
  Physical resource: U0/Mmult_n0340/CLK
  Logical resource: U0/Mmult_n0340/CLK
  Location pin: DSP48_X1Y38.CLK
  Clock network: ap_clk
--------------------------------------------------------------------------------
Slack: -0.809ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 2.809ns (355.999MHz) (Tdspper_AREG_PREG_MULT)
  Physical resource: U0/Mmult_n0370/CLK
  Logical resource: U0/Mmult_n0370/CLK
  Location pin: DSP48_X1Y39.CLK
  Clock network: ap_clk
--------------------------------------------------------------------------------

只看该作者 · 2011-8-2 22:21

顶起

只看该作者 · 2011-8-2 22:36

官网有一个比较详细的解释.
http://china.xilinx.com/support/answers/32109.htm

顺便把内容也贴一下:
Question:

When analyzing my Period constraint, I receive a Component Switching Limit errors on a PERIOD constraint. I should be within specifications.

Why do I see these errors?

Solution:

The Component Switching Limits can be different than the limits defined in the Datasheet, when a TEMPERATURE and/or VOLTAGE constraint is applied to the design. We have seen situations where changing the VOLTAGE constraint in the UCF will change the Component Switching Limit MAX/MIN frequencies.

The VOLTAGE and TEMPERATURE constraints are not supposed to change Component Switching Limits. This is a bug and is to be fixed in the next major release of the tools.

Make sure that you understand the component switching limit that you are seeing. The analysis below shows a violation on a source constraint for a given component. To identify where the violation is occurring, look at the "Location pin: DCM_ADV_X0Y1.CLKIN". In the following example the problem is associated with the DCM_ADV, not an IBUFG or any other components in the clock path:

================================================================================
Timing constraint: NET "Clk" PERIOD = 1 ns HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
7 timing errors detected. (7 component switching limit errors)
Minimum period is 6.666ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: NET "Clk" PERIOD = 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpc)
Physical resource: dll0/CLKIN
Logical resource: dll0/CLKIN
Location pin: DCM_ADV_X0Y1.CLKIN
Clock network: Clk
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpco)
Physical resource: dll0/CLK0
Logical resource: dll0/CLK0
Location pin: DCM_ADV_X0Y1.CLK0
Clock network: Clk0A
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpc)
Physical resource: dll1/CLKIN
Logical resource: dll1/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: Clk
--------------------------------------------------------------------------------