TMS320C6748 无法正常启动，PSC0和PSC1过程出错，或DDR 启动异常原因为何？

只看该作者 · 2018-7-9 22:56

TMS320C6748核心板，采用3路独立电源供电，上电次序依次为+5V、+1.3V、+1.8V和3.3V，各个电源上电的时间间隔在200us左右，采用24MHz无源晶振，实测晶振正常起振，输出24MHz时钟信号，复位芯片采用tps3808g33dbvr，在3.3V正常供电后保持200ms低电平以供CPU复位，采用CC6.0平台进行编译时，报错

PSC0 Enable Transition Timeout on Domain 0 ,LPSC0

PSC0 Enable Verify Timeout on Domain 0,LPSC0

PSC0 Enable Transition Timeout on Domain 0,LPSC1

PSC0 Enable Verify Timeout on Domain 0,LPSC1

PSC0 Enable Transition Timeout on Domain 0,LPSC2

PSC0 Enable Verify Timeout on Domain 0,LPSC2

PSC0 Enable Transition Timeout on Domain 0,LPSC3

PSC0 Enable Verify Timeout on Domain 0,LPSC3

PSC0 Enable Transition Timeout on Domain 0,LPSC4

PSC0 Enable Verify Timeout on Domain 0,LPSC4

PSC0 Enable Transition Timeout on Domain 0,LPSC5

PSC0 Enable Verify Timeout on Domain 0,LPSC5

PSC0 Enable Transition Timeout on Domain 0,LPSC9

PSC0 Enable Verify Timeout on Domain 0,LPSC9

PSC1 Enable Transition Timeout on Domain 0,LPSC0

PSC1 Enable Verify Timeout on Domain 0,LPSC0

PSC1 Enable Transition Timeout on Domain 0,LPSC1

PSC1 Enable Verify Timeout on Domain 0,LPSC1

PSC1 Enable Transition Timeout on Domain 0,LPSC2

PSC1 Enable Verify Timeout on Domain 0,LPSC2

......

PSC1 Enable Transition Timeout on Domain 0,LPSC21

PSC1 Enable Verify Timeout on Domain 0,LPSC21

PSC1 Enable Transition Timeout on Domain 0,LPSC31

PSC1 Enable Verify Timeout on Domain 0,LPSC31

PSC Enable

---------------------------------------------------------------------------

PLL0 init done for Core:456MHz,EMIFA:45MHz

DDR initialization is in progress...

--------------------------------------------------------------------------

C674x_0:Trouble Reading Memory Block at 0x1c188 on Page 0 of Length 0x4:(Error-1178@0x1C14188 ) Device functional clock

configuration and/or try more reliable JTAG(e.g.lower TCLK)(Emulation package 5.1.507.0)

C674X_0:GEL:Eror while executing OntargetConnect():Target failed to read 0x01C14188 at(*(unsigned int*)(0x01C141000))

2) [TH8300.gel:439] at Set_ DDRPLL_156MHz()

[TH8300.gel.447]  at Set_DDR2_156MHz()

[TH8300.gel.454]  at Core_456MHz_DDR2

at OnTargetconnect().

C674X_0:Trouble Reading Register CSR:(Error-1178@0x41)Device functional clock appears to be off.

            Power-cycle the board.......

C674X_0:Trouble Writing Memory Block at 0xc0000000 on Page 0 of Length 0x80:(Error-1178@0x41188)Device functional clock

         configuration and/or try more reliable JTAG(e.g.lower TCLK)(Emulation package 5.1.507.0)

C674X_0:GEl:File:D:\TH8300_prj_dsp\TH8300_prj\TH8300\Debug\TH8300.out:Load Failed