#include <stdio.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_chip.h>
#include <csl_mcbsp.h>
#include <csl_gpio.h>
#include <csl_mcbsphal.h>
/*typedef struct {
Uint32 spcr;
Uint32 rcr;
Uint32 xcr;
Uint32 srgr;
Uint32 mcr;
Uint32 rcer;
Uint32 xcer;
Uint32 pcr;
} MCBSP_Config;*/
//将SPCR中的RRST 和XRST 位清0，禁止缓冲串口发送和接收数据，然后将PCR的
//RIOEN和XIOEN位置1，就将所有的缓冲串口引脚配置成通用I/O口。
static MCBSP_Config MyMcbspConfig =
{
MCBSP_SPCR_RMK //Serial Port Control Register (SPCR) ???????
(
MCBSP_SPCR_FREE_YES, // Serial clock free running mode(FREE)
MCBSP_SPCR_SOFT_YES, // Serial clock emulation mode(SOFT)
MCBSP_SPCR_FRST_YES, // Frame sync generator reset(FRST)
MCBSP_SPCR_GRST_YES, // Sample rate generator reset(GRST)
MCBSP_SPCR_XINTM_XRDY, // Transmit interrupt mode(XINTM)
MCBSP_SPCR_XSYNCERR_NO, // Transmit synchronization error
MCBSP_SPCR_XRST_0 , // 禁止缓冲串口发送数据
MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode
MCBSP_SPCR_RJUST_LZF, // Receive data sign-extension and
// justification mode(RJUST)
MCBSP_SPCR_CLKSTP_DISABLE, // Clock stop(CLKSTP) mode
MCBSP_SPCR_DXENA_ON, // DX Enabler(DXENA) -Extra delay for
// DX turn-on time.
MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode
MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR)
MCBSP_SPCR_RRST_0 // 禁止缓冲串口接收数据
),
MCBSP_RCR_RMK // Receive Control Register (RCR)
(
MCBSP_RCR_RPHASE_SINGLE, // Receive phases
MCBSP_RCR_RFRLEN2_OF(0), // Receive frame length
// in phase 2(RFRLEN2)
MCBSP_RCR_RWDLEN2_32BIT, // Receive element length
// in phase 2(RWDLEN2)
MCBSP_RCR_RCOMPAND_MSB, // Receive companding mode (RCOMPAND)
MCBSP_RCR_RFIG_NO, // Receive frame ignore(RFIG)
MCBSP_RCR_RDATDLY_0BIT, // Receive data delay(RDATDLY)
MCBSP_RCR_RFRLEN1_OF(1), // Receive frame length
// in phase 1(RFRLEN1)
MCBSP_RCR_RWDLEN1_32BIT, // Receive element length
// in phase 1(RWDLEN1)
MCBSP_RCR_RWDREVRS_DISABLE // Receive 32-bit bit reversal
// feature.(RWDREVRS)
),
MCBSP_XCR_RMK //Transmit Control Register (XCR)
(
MCBSP_XCR_XPHASE_SINGLE, // Transmit phases
MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length
// in phase 2(XFRLEN2)
MCBSP_XCR_XWDLEN2_32BIT, // Transmit element length
// in phase 2
MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND)
MCBSP_XCR_XFIG_NO, // Transmit frame ignore(XFIG)
MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY)
MCBSP_XCR_XFRLEN1_OF(1), // Transmit frame length
// in phase 1(XFRLEN1)
MCBSP_XCR_XWDLEN1_32BIT, // Transmit element length
// in phase 1(XWDLEN1)
MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature
),
/* MCBSP_SRGR_RMK //serial port sample rate generator register(SRGR)
(
MCBSP_SRGR_GSYNC_FREE, // Sample rate generator clock
// synchronization(GSYNC).
MCBSP_SRGR_CLKSP_RISING, // CLKS polarity clock edge select(CLKSP)
MCBSP_SRGR_CLKSM_INTERNAL, // MCBSP sample rate generator clock
// mode(CLKSM)
MCBSP_SRGR_FSGM_DXR2XSR, // Sample rate generator transmit frame
// synchronization
MCBSP_SRGR_FPER_OF(63), // Frame period(FPER)
MCBSP_SRGR_FWID_OF(31), // Frame width(FWID)
MCBSP_SRGR_CLKGDV_OF(15) // Sample rate generator clock
// divider(CLKGDV)
),*/
MCBSP_SRGR_DEFAULT,
MCBSP_MCR_DEFAULT, // Using default value of MCR register
MCBSP_RCERE0_DEFAULT, // Using default value of RCERE registers
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
MCBSP_XCERE0_DEFAULT, // Using default value of XCERE registers
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,
MCBSP_PCR_RMK //serial port pin control register(PCR)
(
MCBSP_PCR_XIOEN_GPIO, // Transmitter in general-purpose I/O mode
MCBSP_PCR_RIOEN_GPIO, // Receiver in general-purpose I/O mode
MCBSP_PCR_FSXM_EXTERNAL, // Transmit frame synchronization mode
MCBSP_PCR_FSRM_EXTERNAL, // Receive frame synchronization mode
MCBSP_PCR_CLKXM_OUTPUT, // 引脚CLKX输出使能位
MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM)
MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT)
MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT)
MCBSP_PCR_FSXP_ACTIVEHIGH, // Transmit frame synchronization polarity(FSXP)
MCBSP_PCR_FSRP_ACTIVEHIGH, // Receive frame synchronization polarity(FSRP)
MCBSP_PCR_CLKXP_FALLING, // Transmit clock polarity(CLKXP)
MCBSP_PCR_CLKRP_RISING // Receive clock polarity(CLKRP)
)
};
MCBSP_Handle hMcbsp;
void main()
{
CSL_init();
//Open up serial port 0
hMcbsp = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
MyMcbspConfig.pcr=0x00000200;//输出为低电平
// MyMcbspConfig.pcr=0x00000202;//输出为高电平
//Configure McBSP for digital loopback, 32bit mode
// and setup the sample rate generator to allow self clocking
MCBSP_config(hMcbsp, &MyMcbspConfig);
//Enable McBSP in steps
MCBSP_start(hMcbsp,
MCBSP_RCV_START | MCBSP_XMIT_START,
0);
}
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