用cpld器件，verilog编程很容易实现。其verilog代码如下：
module dff1000(clk, out);
input clk;
output out;
reg out;
reg [10:0] count;
initial
count = 10'h3E8; // 1000
alway @ (posedge clk)
if(count)
begin
count <= count - 1;
if(count > (10'h3E8 - 8'hFA)) // count > (1000 - 250)
out <= 1;
else
out <= 0;
end
else
begin
count <= 10'h3E8; // 1000
out <= 1;
end
endmodule
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楼主
