编译后时序有错误，下面这种错误怎么解决呢？

只看该作者 · 2018-10-11 17:48

这是一部分时序报错提示

Timing constraint: TS_PLLx_1_clkout1_0 = PERIOD TIMEGRP "PLLx_1_clkout1_0" TS_CLK25M_P / 10 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612). 114557 paths analyzed, 39840 endpoints analyzed, 1161 failing endpoints 1161 timing errors detected. (1161 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 7.627ns. -------------------------------------------------------------------------------- Paths for end point inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2 (SLICE_X36Y131.D5), 14 paths -------------------------------------------------------------------------------- Slack (setup path): -3.627ns (requirement - (data path - clock path skew + uncertainty)) Source: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0[/url] (FF) Destination: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] (FF) Requirement: 4.000ns Data Path Delay: 7.075ns (Levels of Logic = 4) Clock Path Skew: -0.426ns (0.736 - 1.162) Source Clock: clk125m rising at 0.000ns Destination Clock: clk125m rising at 4.000ns Clock Uncertainty: 0.126ns Clock Uncertainty: 0.126ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.242ns Phase Error (PE): 0.000ns [url=CPPath^Maximum Data Path at Slow Process Corner: inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0 to inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,0.408,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd[0],4.179,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0,0.259,Net,N1008,0.327,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.656,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token,0.387,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]Maximum Data Path at Slow Process Corner: inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0 to inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X66Y182.AQ Tcko 0.408 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd[0] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,0.408^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,0.408]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0[/url] SLICE_X41Y136.C5 net (fanout=3) 4.179 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd[0]^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_0,0.408,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd[0],4.179,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd[0][/url] SLICE_X41Y136.C Tilo 0.259 N1008 [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0,0.259^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0[/url] SLICE_X41Y136.B4 net (fanout=1) 0.327 [url=CPNetPath^N1008^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1_SW0,0.259,Net,N1008,0.327,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259]N1008[/url] SLICE_X41Y136.B Tilo 0.259 N1008 [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1[/url] SLICE_X37Y132.A5 net (fanout=5) 0.656 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.656,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1[/url] SLICE_X37Y132.A Tilo 0.259 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt[0] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2[/url] SLICE_X36Y131.D5 net (fanout=5) 0.387 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token,0.387,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token[/url] SLICE_X36Y131.CLK Tas 0.341 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt[2] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3[/url] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] ------------------------------------------------- --------------------------- Total 7.075ns (1.526ns logic, 5.549ns route) (21.6% logic, 78.4% route) -------------------------------------------------------------------------------- Slack (setup path): -0.317ns (requirement - (data path - clock path skew + uncertainty)) Source: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4[/url] (FF) Destination: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] (FF) Requirement: 4.000ns Data Path Delay: 4.183ns (Levels of Logic = 4) Clock Path Skew: -0.008ns (0.249 - 0.257) Source Clock: clk125m rising at 0.000ns Destination Clock: clk125m rising at 4.000ns Clock Uncertainty: 0.126ns Clock Uncertainty: 0.126ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.242ns Phase Error (PE): 0.000ns [url=CPPath^Maximum Data Path at Slow Process Corner: inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4 to inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.408,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.792,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1,0.313,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rec_idle_sig,0.768,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.656,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token,0.387,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]Maximum Data Path at Slow Process Corner: inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4 to inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X40Y134.CQ Tcko 0.408 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4 [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.408^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.408]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4[/url] SLICE_X37Y129.C5 net (fanout=18) 0.792 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.408,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4,0.792,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1,0.313]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_FSM_FFd4[/url] SLICE_X37Y129.CMUX Tilo 0.313 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rx_data_7 [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1,0.313^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1,0.313]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1[/url] SLICE_X41Y136.B6 net (fanout=5) 0.768 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rec_idle_sig^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/recieve_st_rec_idle_sig1,0.313,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rec_idle_sig,0.768,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rec_idle_sig[/url] SLICE_X41Y136.B Tilo 0.259 N1008 [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1[/url] SLICE_X37Y132.A5 net (fanout=5) 0.656 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1,0.656,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token1[/url] SLICE_X37Y132.A Tilo 0.259 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt[0] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2[/url] SLICE_X36Y131.D5 net (fanout=5) 0.387 [url=CPNetPath^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token^Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/idle_token2,0.259,Net,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token,0.387,Bel,inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/idle_token[/url] SLICE_X36Y131.CLK Tas 0.341 inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt[2] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3,0.341]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/Mmux_curr_st[1]_rcnt[3]_wide_mux_62_OUT3[/url] [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] ------------------------------------------------- --------------------------- Total 4.183ns (1.580ns logic, 2.603ns route) (37.8% logic, 62.2% route) -------------------------------------------------------------------------------- Slack (setup path): -0.289ns (requirement - (data path - clock path skew + uncertainty)) Source: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_4,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_4,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/ser2par_dec0/shd_4[/url] (FF) Destination: [url=CPBel^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA^inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2,NA]inst_comm[21].Inst_hdlc_module_i/hdlc_dec/rcnt_2[/url] (FF) Requirement: 4.000ns Data Path Delay: 4.120ns (Levels of Logic = 4) Clock Path Skew: -0.043ns (0.736 - 0.779) Source Clock: clk125m rising at 0.000ns Destination Clock: clk125m rising at 4.000ns Clock Uncertainty: 0.126ns Clock Uncertainty: 0.126ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.242ns Phase Error (PE): 0.000ns

编译后时序有错误，下面这种错误怎么解决呢？

相关下载

相关帖子