ISE EDK 编译的怪问题！（经过一天奋战，终于解决...）

只看该作者 · 2011-8-21 09:54

本帖最后由 avonhu 于 2011-8-21 18:04 编辑

这几天想调试一下板子，建了一个ISE工程，包含一个嵌入式微处理器，结果在EDK中调用： Hardware->Generate Netlist的时候，出现了如下的怪问题
ERROR:HDLParsers:3582 - Error opening "xst/plbv46_slave_single_v1_01_a/hdpdeps.ref" for reading.
ERROR:HDLParsers:3582 - Error opening "xst/xps_uartlite_v1_02_a/hdpdeps.ref" for reading.
ERROR:EDK:546 - Aborting XST flow execution!
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/dlmb_wrapper.ngc]

而且出错模块不稳定，应该和IP核没什么关系
ERROR:HDLParsers:3582 - Error opening "xst/interrupt_control_v2_01_a/hdpdeps.ref" for reading.
ERROR:EDK:546 - Aborting XST flow execution!
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/leds_8bit_wrapper.ngc]

是不是哪里设置的问题呢？我用的Windows 7, ISE SUITE 13.2
死活都通不过！求高手解惑！

只看该作者 · 2011-8-21 10:01

自己先顶一个！

只看该作者 · 2011-8-21 10:29

补充信息，通过跟踪platgen.log文件，发现是编译ps2_keyboard_wrap...时出问题的，以下是srp文件
Release 13.2 - xst O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
   5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
   6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT

=========================================================================
*                   Synthesis Options Summary                      *
=========================================================================
---- Source Parameters
Input Format                      : MIXED
Input File Name                   : "ps2_keyboard_wrapper_xst.prj"
Verilog Include Directory       : {"E:\MyDesigns\MyFPGA\ISE\XUPTEST\Version132\NetFPGA\NetCPU\pcores\" "D:\Xilinx132\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\"
                                 "D:\Xilinx132\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                   : xc5vlx110tff1136-1
Output File Name                : "../implementation/ps2_keyboard_wrapper.ngc"

---- Source Options
Top Module Name                   : ps2_keyboard_wrapper

---- Target Options
Add IO Buffers                   : NO

---- General Options
Optimization Goal                : speed
Netlist Hierarchy                : as_optimized
Optimization Effort             : 1
Hierarchy Separator             : /

---- Other Options
Cores Search Directories          : {../implementation}

=========================================================================

=========================================================================
*                         HDL Compilation                            *
=========================================================================
ERROR:HDLParsers:3582 - Error opening "xst/plbv46_slave_single_v1_01_a/hdpdeps.ref" for reading.
-->

Total memory usage is 203936 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

只看该作者 · 2011-8-21 11:32

修改用户环境变量，继续测试！
TEMP由c:\windows\temp修改为C:\TEMP，因为编译提示TEMP环境变量没有设置或指向了一个没有写入权限的文件夹。
正在编译ing...

只看该作者 · 2011-8-21 11:34

编译到ddr2_sdram核出问题了...以下是ddr2_sdram_wrap_xst.srp报告文件
Release 13.2 - xst O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
   5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
   6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT

=========================================================================
*                   Synthesis Options Summary                      *
=========================================================================
---- Source Parameters
Input Format                      : MIXED
Input File Name                   : "ddr2_sdram_wrapper_xst.prj"
Verilog Include Directory       : {"E:\MyDesigns\MyFPGA\ISE\XUPTEST\Version132\NetFPGA\NetCPU\pcores\" "D:\Xilinx132\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\" "D:\Xilinx132\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                   : xc5vlx110tff1136-1
Output File Name                : "../implementation/ddr2_sdram_wrapper.ngc"

---- Source Options
Top Module Name                   : ddr2_sdram_wrapper

---- Target Options
Add IO Buffers                   : NO

---- General Options
Optimization Goal                : speed
Netlist Hierarchy                : as_optimized
Optimization Effort             : 1
Hierarchy Separator             : /

---- Other Options
Cores Search Directories          : {../implementation}

=========================================================================

=========================================================================
*                         HDL Compilation                            *
=========================================================================
ERROR:HDLParsers:3582 - Error opening "xst/proc_common_v3_00_a/hdpdeps.ref" for reading.
-->

Total memory usage is 205088 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

只看该作者 · 2011-8-21 11:39

下午继续！吃饭去咯...

只看该作者 · 2011-8-21 14:43

怎么这个帖子成我自编自导的啦！

只看该作者 · 2011-8-21 15:00

本帖最后由 avonhu 于 2011-8-21 15:13 编辑

应该不是许可证的问题吧？我使用网上搜来的许可证生成器：

只看该作者 · 2011-8-21 15:11

本帖最后由 avonhu 于 2011-8-21 15:13 编辑

还是不行啊！而且出错模块又变了！！！
这是EDK编译的log文件片段：
INSTANCE:hard_ethernet_mac_fifo -
E:\MyDesigns\MyFPGA\ISE\XUPTEST\Version132\NetFPGA\NetCPU\NetCPU.mhs line 389 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
ERROR:HDLParsers:3582 - Error opening "xst/plbv46_slave_burst_v1_01_a/hdpdeps.ref" for reading.
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
E:\MyDesigns\MyFPGA\ISE\XUPTEST\Version132\NetFPGA\NetCPU\synthesis\hard_ethe
rnet_mac_fifo_wrapper_xst.srp for details

以下是上述指示的报告文件：
Release 13.2 - xst O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
   5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
   6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
      9.1) Device utilization summary
      9.2) Partition Resource Summary
      9.3) TIMING REPORT
=========================================================================
*                   Synthesis Options Summary                      *
=========================================================================
---- Source Parameters
Input Format                      : MIXED
Input File Name                   : "hard_ethernet_mac_fifo_wrapper_xst.prj"
Verilog Include Directory       : {"E:\MyDesigns\MyFPGA\ISE\XUPTEST\Version132\NetFPGA\NetCPU\pcores\" "D:\Xilinx132\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\" "D:\Xilinx132\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

-- Target Parameters
Target Device                   : xc5vlx110tff1136-1
Output File Name                : "../implementation/hard_ethernet_mac_fifo_wrapper.ngc"

---- Source Options
Top Module Name                   : hard_ethernet_mac_fifo_wrapper

---- Target Options
Add IO Buffers                   : NO

---- General Options
Optimization Goal                : speed
Netlist Hierarchy                : as_optimized
Optimization Effort             : 1
Hierarchy Separator             : /

---- Other Options
Cores Search Directories          : {../implementation}
=========================================================================
=========================================================================
*                         HDL Compilation                            *
=========================================================================
ERROR:HDLParsers:3582 - Error opening "xst/plbv46_slave_burst_v1_01_a/hdpdeps.ref" for reading.
-->
Total memory usage is 203744 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

诡异啊！诡异...

1万 · 2011-8-21 15:34

权限够么？

只看该作者 · 2011-8-21 15:38

我是以管理员用户登录的啊，权限应该够的啊

只看该作者 · 2011-8-21 15:42

本帖最后由 avonhu 于 2011-8-21 15:43 编辑

刚从别的论坛搜到关于HDLParser出错的问题提示，说有可能是工程文件夹路径太长所致:

现在将工程文件夹拷贝到根目录，清空netlist相关文件，重新编译ing...

只看该作者 · 2011-8-21 15:57

依旧！纠结啊...

只看该作者 · 2011-8-21 17:10

LZ,感觉还是你License的问题.
你打开License Manager看看,确认下License的情况,特别是XPS和你用到的那些IP核

只看该作者 · 2011-8-21 17:16

我下了你的License,运行后发现,只有几个软件的运行许可,但是没有IP核的许可.

只看该作者 · 2011-8-21 17:39

本帖最后由 avonhu 于 2011-8-21 17:41 编辑

这个license的确是用于对ISE SUITE的组件许可，IP核的许可采用的ISE EDK默认的Corelicense许可：
1、EDK\data\core_licenses\xilinx.lic

Xilinx.rar (1.03 KB)
2、ISE\coregen\core_licenses\xilinx.lic , xilinxfree.lic

core_licenses.rar (2.17 KB)

只看该作者 · 2011-8-21 17:50

刚才在ISE中新建了一个含有较少组件的工程，仍然包含一个嵌入式微处理器，不过修改了设计的属性：
如图：
1、将 PreferredLanguage由Verilog改为VHDL
2、将 VHDL Source Analysis Standard由 VHDL-93改为 VHDL-200X

结果Systhesis 通过了！现在按同样方法重新编译原工程，期待ing...

只看该作者 · 2011-8-21 17:52

还在编译，心跳加速ing...

只看该作者 · 2011-8-21 18:02

所有IP核NGC文件建立成功:
Running XST synthesis ...

INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:hard_ethernet_mac - E:\NetFPGA\NetCPU\NetCPU.mhs line 293 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:ddr2_sdram - E:\NetFPGA\NetCPU\NetCPU.mhs line 324 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:sysace_compactflash - E:\NetFPGA\NetCPU\NetCPU.mhs line 362 - Running
XST synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:xps_timer_0 - E:\NetFPGA\NetCPU\NetCPU.mhs line 378 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:hard_ethernet_mac_fifo - E:\NetFPGA\NetCPU\NetCPU.mhs line 389 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:clock_generator_0 - E:\NetFPGA\NetCPU\NetCPU.mhs line 398 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:mdm_0 - E:\NetFPGA\NetCPU\NetCPU.mhs line 433 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:proc_sys_reset_0 - E:\NetFPGA\NetCPU\NetCPU.mhs line 445 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
INSTANCE:xps_intc_0 - E:\NetFPGA\NetCPU\NetCPU.mhs line 458 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Running NGCBUILD ...
IPNAME:hard_ethernet_mac_wrapper INSTANCE:hard_ethernet_mac -
E:\NetFPGA\NetCPU\NetCPU.mhs line 293 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Command Line: d:\Xilinx132\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vlx110tff1136-1 -intstyle silent -i -sd .. hard_ethernet_mac_wrapper.ngc
../hard_ethernet_mac_wrapper
Reading NGO file
"E:/NetFPGA/NetCPU/implementation/hard_ethernet_mac_wrapper/hard_ethernet_mac_wr
apper.ngc" ...
Executing edif2ngd -noa
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper_fifo_generator_v4_3_
1.edn" "hard_ethernet_mac_wrapper_fifo_generator_v4_3_1.ngo"
Release 13.2 - edif2ngd O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 13.2 edif2ngd O.61xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <D:/Xilinx132/ISE_DS/EDK/data/edif2ngd.pfd>
with local file <d:/Xilinx132/ISE_DS/ISE/data/edif2ngd.pfd>
Writing module to "hard_ethernet_mac_wrapper_fifo_generator_v4_3_1.ngo"...
Loading design module
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper\hard_ethernet_mac_wr
apper_fifo_generator_v4_3_1.ngo"...
Loading design module
"../hard_ethernet_mac_wrapper_fifo_generator_v4_3_1_fifo_generator_v4_3_xst_1.ng
c"...
Executing edif2ngd -noa
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper_fifo_generator_v4_3_
2.edn" "hard_ethernet_mac_wrapper_fifo_generator_v4_3_2.ngo"
Release 13.2 - edif2ngd O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 13.2 edif2ngd O.61xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <D:/Xilinx132/ISE_DS/EDK/data/edif2ngd.pfd>
with local file <d:/Xilinx132/ISE_DS/ISE/data/edif2ngd.pfd>
Writing module to "hard_ethernet_mac_wrapper_fifo_generator_v4_3_2.ngo"...
Loading design module
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper\hard_ethernet_mac_wr
apper_fifo_generator_v4_3_2.ngo"...
Loading design module
"../hard_ethernet_mac_wrapper_fifo_generator_v4_3_2_fifo_generator_v4_3_xst_1.ng
c"...
Executing edif2ngd -noa
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper_fifo_generator_v4_3_
4.edn" "hard_ethernet_mac_wrapper_fifo_generator_v4_3_4.ngo"
Release 13.2 - edif2ngd O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 13.2 edif2ngd O.61xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <D:/Xilinx132/ISE_DS/EDK/data/edif2ngd.pfd>
with local file <d:/Xilinx132/ISE_DS/ISE/data/edif2ngd.pfd>
Writing module to "hard_ethernet_mac_wrapper_fifo_generator_v4_3_4.ngo"...
Loading design module
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper\hard_ethernet_mac_wr
apper_fifo_generator_v4_3_4.ngo"...
Loading design module
"../hard_ethernet_mac_wrapper_fifo_generator_v4_3_4_fifo_generator_v4_3_xst_1.ng
c"...
Executing edif2ngd -noa
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper_fifo_generator_v4_3_
3.edn" "hard_ethernet_mac_wrapper_fifo_generator_v4_3_3.ngo"
Release 13.2 - edif2ngd O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 13.2 edif2ngd O.61xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <D:/Xilinx132/ISE_DS/EDK/data/edif2ngd.pfd>
with local file <d:/Xilinx132/ISE_DS/ISE/data/edif2ngd.pfd>
Writing module to "hard_ethernet_mac_wrapper_fifo_generator_v4_3_3.ngo"...
Loading design module
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper\hard_ethernet_mac_wr
apper_fifo_generator_v4_3_3.ngo"...
Loading design module
"../hard_ethernet_mac_wrapper_fifo_generator_v4_3_3_fifo_generator_v4_3_xst_1.ng
c"...
Executing edif2ngd -noa
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper_blk_mem_gen_v2_7.edn
" "hard_ethernet_mac_wrapper_blk_mem_gen_v2_7.ngo"
Release 13.2 - edif2ngd O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 13.2 edif2ngd O.61xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <D:/Xilinx132/ISE_DS/EDK/data/edif2ngd.pfd>
with local file <d:/Xilinx132/ISE_DS/ISE/data/edif2ngd.pfd>
Writing module to "hard_ethernet_mac_wrapper_blk_mem_gen_v2_7.ngo"...
Loading design module
"E:\NetFPGA\NetCPU\implementation\hard_ethernet_mac_wrapper\hard_ethernet_mac_wr
apper_blk_mem_gen_v2_7.ngo"...
Loading design module
"../hard_ethernet_mac_wrapper_blk_mem_gen_v2_7_blk_mem_gen_v2_7_xst_1.ngc"...
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:    0
  Number of warnings: 0
Writing NGC file "../hard_ethernet_mac_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  10 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../hard_ethernet_mac_wrapper.blc"...
NGCBUILD done.
IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram - E:\NetFPGA\NetCPU\NetCPU.mhs
line 324 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Command Line: d:\Xilinx132\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vlx110tff1136-1 -intstyle silent -i -sd .. ddr2_sdram_wrapper.ngc
../ddr2_sdram_wrapper
Reading NGO file
"E:/NetFPGA/NetCPU/implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:    0
  Number of warnings: 0
Writing NGC file "../ddr2_sdram_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...
NGCBUILD done.
IPNAME:hard_ethernet_mac_fifo_wrapper INSTANCE:hard_ethernet_mac_fifo -
E:\NetFPGA\NetCPU\NetCPU.mhs line 389 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Command Line: d:\Xilinx132\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vlx110tff1136-1 -intstyle silent -i -sd .. hard_ethernet_mac_fifo_wrapper.ngc
../hard_ethernet_mac_fifo_wrapper
Reading NGO file
"E:/NetFPGA/NetCPU/implementation/hard_ethernet_mac_fifo_wrapper/hard_ethernet_m
ac_fifo_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:    0
  Number of warnings: 0
Writing NGC file "../hard_ethernet_mac_fifo_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../hard_ethernet_mac_fifo_wrapper.blc"...
NGCBUILD done.
IPNAME:clock_generator_0_wrapper INSTANCE:clock_generator_0 -
E:\NetFPGA\NetCPU\NetCPU.mhs line 398 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Command Line: d:\Xilinx132\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vlx110tff1136-1 -intstyle silent -i -sd .. clock_generator_0_wrapper.ngc
../clock_generator_0_wrapper
Reading NGO file
"E:/NetFPGA/NetCPU/implementation/clock_generator_0_wrapper/clock_generator_0_wr
apper.ngc" ...
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:    0
  Number of warnings: 0
Writing NGC file "../clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 - E:\NetFPGA\NetCPU\NetCPU.mhs
line 458 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
Command Line: d:\Xilinx132\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vlx110tff1136-1 -intstyle silent -i -sd .. xps_intc_0_wrapper.ngc
../xps_intc_0_wrapper
Reading NGO file
"E:/NetFPGA/NetCPU/implementation/xps_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:    0
  Number of warnings: 0
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
NGCBUILD done.
希望就在前头，继续等待最后结果...

只看该作者 · 2011-8-21 18:03

哈哈...成功了！
"Running synthesis..."
cd synthesis & synthesis.cmd
"xst -ifn "NetCPU_xst.scr" -intstyle silent"
"Running XST synthesis ..."
PMSPEC -- Overriding Xilinx file
<D:/Xilinx132/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
<d:/Xilinx132/ISE_DS/ISE/virtex5/data/virtex5.acd>
"XST completed"
Done!
问题终于解决！不过...大侠们懂的！

ISE EDK 编译的怪问题！（经过一天奋战，终于解决...）

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