module cpu(clk,rst,rd,wr,addr,data,opcode,fetch,ir_addr,pc_addr);
input clk,rst;
output rd,wr;
output[4:0]addr;
output[2:0]opcode;
output fetch;
output[4:0]ir_addr,pc_addr;
inout[7:0]data;
wire clk,rst;
wire[7:0] data;
wire[4:0]addr;
wire rd,wr;
wire fetch,alu_ena;
wire[2:0] opcode;
wire[4:0] ir_addr,pc_addr;
wire[7:0] alu_out,accum;
wire zero,inc_pc,load_acc,load_pc,load_ir;
register m_register (.data(data),.load_ir(load_ir),.rst(rst),.clk(clk),.opcode(opcode),.ir_addr(ir_addr));
accum m_accum (.data(alu_out),.load_acc(load_acc),.clk(clk),.rst(rst),.accum(accum));
alu m_alu (.zero(zero),.data(data),.accum(accum),.clk(clk),.opcode(opcode),.alu_out(alu_out));
machine m_machine (.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),.load_dr(load_dr),.rst(rst),.fetch(fetch),.rd(rd),.wr(wr),.clk(clk),.load_ir(load_ir),.zero(zero),.opcode(opcode));
adr m_addrchoose (.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr));
counter m_counter (.inc_pc(inc_pc),.rst(rst),.ir_addr(ir_addr),.load_pc(load_pc),.pc_addr(pc_addr));
fetch m_fetch (.clk(clk),.rst(rst),.fetch(fetch));
dr m_dr (.data(data),.alu_out(alu_out),.clk(clk),.rst(rst),.load_dr(load_dr));
endmodule
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