1. 各通道有独立的时钟源(TMR0_CLK, TMR1_CLK, TMR2_CLK, TMR3_CLK)
时间溢出周期= (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)
最大计数周期= (1 / 25 MHz) * (2^8) * (2^24), if TCLK = 25 MHz
8位预分频计数器,带24位向上计数定时器
内部24位定时器的值,通过TDR(定时器数据寄存器)可读取 2. 每个通道带一个8位预分频计数器,一个24位向上计数器,一个24位比较寄存器和一个中断请求信号. 3.
4.定时器模式 #define TIMER_ONESHOT_MODE (0UL << TIMER_TCSR_MODE_Pos)
#define TIMER_PERIODIC_MODE (1UL << TIMER_TCSR_MODE_Pos)
#define TIMER_TOGGLE_MODE (2UL << TIMER_TCSR_MODE_Pos)
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos)
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos)
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_TEXCON_RSTCAPSEL_Pos)
#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_TEXCON_RSTCAPSEL_Pos)
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