本帖最后由 Go_PSoC 于 2011-9-7 23:12 编辑
| 赛普拉斯Cypress2012应届硕士毕业生招聘 | |
2012年赛普拉斯cypress面向应届硕士毕业生招聘职位分别是：Application Engineer，ASIC Design Engineer，ASIC Verification Engineer，工作地点有上海也有深圳，如果你有意向请别错过，请发简历到rwei@cypress.com， 简历请注明成绩和排名，赛普拉斯真诚欢迎各位优秀毕业生的到来。以下是个职位详细介绍：
Job Title: Application Engineer (New College Graduate)
Location: Shenzhen
Job Description:
Developing solutions by award-winning Cypress PSoC(programmable SoC) and other silicon
Developing HW/FW according to key customer’s new product concepts
Developing reference design, evaluation kits, development kits for new IC chips
Technical support to marketing colleagues on new application exploration
Other application related technical support to IC engineer, Sales, FAE etc,
Switch to AE or FAE position according to personal interesting after 1 year training
Job Requirements:
Excellent fundamental knowledge on both analog and digital circuit
Solid “C” and assembly language
Experience on at least 2 CPUs among MCU, ARM, DSP etc,
Experience on I2C, SPI, RS232 and other MCU related interfaces
Fluent in English (as working language)
Smart, honest, innovative and confident
Initiative and goal-driven
Customer service orientated
Minimum Education & Work Experience:
Major in EE/CE or related
Bachelor Degree with 1-2 years working experience OR,
new graduates with master degree
Benefits:
Competitive salary and stock options
Excellent medical insurance plan
New product revenue bonus
Extensive training programs covering both technology and management skills
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Job title: Applications Engineer
Job Description:
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Provide Technical Support to Cypress Products (Programmable System On Chip (PSoC), Memory, USB, Clocks, Ext.) customers via Online case management system by debugging customer’s Electronic hardware, firmware and software issues.
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Provide self and customer feedback on Documentation, Development Tools, and Silicon to appropriate teams.
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Create High Quality Content - Knowledge Base, FAQ’s, White Papers, Technical Briefs and Articles, Example projects, Application notes.
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Training for Customers / Partners.
Job Requirements:
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Good embedded microcontroller (8-bit, 16-bit, 32-bit)/embedded control application familiarity.
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Ability to analyze and debug analog, digital and micro-controller circuits.
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Ability to write and debug software in C and/or assembler.
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Good Communication Skills.
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Good English and Mandarin skills– Verbal and Written.
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Ability to multi-task, Thrive on Problem Solving.
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Good team player - work in cross-functional teams involving designers, software developers, product test and assembly engineers.
Minimum Education & Work Experience :
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New College Graduates
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Master Degree in EE/CE
Benefits:
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Competitive salary
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Excellent social insurance plan
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Quarterly performance bonus
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Extensive training programs covering both technology and management skills
Work location: Zhangjiang Shanghai, China
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Job Title:ASIC Design Engineer
Job Description:
As a logic designer, will be responsible for IP and full-chip RTL/logic design. He will be involved in all phases of the development, including spec definition, RTL coding, verification closure, synthesis, DFT, STA, etc.
Summary of Duties/Responsibilities:
Design Spec Definition: after get marketing requirement, be able to convert it into design spec with feature list, block diagram, input/output definition, performance analysis, die size estimation, etc. IP design: be able conduct feasibility study, micro-architecture design, and RTL coding Digital IC BE implementation: be able to run synthesis and DFT insertion tool with power aware constraints,
need to analysis synthesis log and dft coverage using ATPG tool, Will be involved in STA for timing sign-off, - Will work with verification engineer to setup verification plan, and debug for verification closure.
Job Requirements:
Very good English skills Hard working and team player Takes initiative and sets high goals Smart and confident Self starter & ability to work in a team environment as an individual contributor - Track record of planning and delivering own work completely and on time
Education & Work Experience:
Master’s Degree or above in EE/CE Experience with Verilog logic design is a must Experience with synthesis/sta tool is a must Proficiency in one of script language, such as Perl, Tcl, will be a plus Experience with logic verification will be a plus,
- Knowledge of ARM CPU, AMBA bus, I2C/SPI/UART interface will be a plus,
Benefits:
Competitive salary Stock options Excellent medical insurance plan New product revenue bonus - Extensive training programs covering both technology and management skills
Location:Shanghai, China
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Job Title:ASIC Verification Engineer
Job Description:
Will be a member of logic verification team. Primary responsibility will be test bench development and verification of RTL logic designs. He will also be involved in the development of industry leading-edge OVM/UVM verification methodology for Cypress PSoC product
Summary of Duties/Responsibilities:
Requirements analysis. Must be able to effectively reduce system and IC module specifications into written verification requirements (development of verification plans, detailed specifications, test bench functional requirements, test vectors, etc.) Design of System-Verilog/OVM test benches for efficient and flexible use by self and others. Verification of RTL logic designs and reporting of functional simulation and code coverage results. Assist logic/RTL designers with debug efforts to achieve full functionality and code coverage metrics of IC designs. Document test bench designs and participate in design reviews in accordance with department development process and company quality standards. - Test bench support, maintenance and user training.
Job Requirements:
Very good English skills Hard working and team player Takes initiative and sets high goals Smart and confident - Self starter & ability to work in a team environment as an individual contributor
Education & Work Experience:
Master’s Degree or above in EE/CE Proficiency in one of script language, such as Perl, Tcl Experience with Verilog logic design is a must Experience with test bench development and behavioral functional model development is a must,
Knowledge of ARM CPU, AMBA bus, I2C/SPI/UART interface will be a plus, Familiar with System-Verilog will be a big plus - Experience with VMM/OVM/UVM will be a big plus
Benefits:
Competitive salary Stock options Excellent medical insurance plan New product revenue bonus - Extensive training programs covering both technology and management skills
Location:Shanghai, China
有意者请发简历到：rwei@cypress.com，简历请注明成绩和排名
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