modelsim 仿真ip core

只看该作者 · 2011-9-23 21:28

如题，我在弄。但是出问题了。我也看了网上说加库什么的，我都加了，
这个是错误的原因：
# ** Error: D:/Xilinx92i/practice02/mydds.v(349): Module 'C_GATE_BIT_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(437): Module 'C_REG_FD_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(582): Module 'C_ADDSUB_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(627): Module 'C_REG_FD_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(672): Module 'C_REG_FD_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(691): Module 'LUT4' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(710): Module 'LUT4' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(876): Module 'BLKMEMDP_V6_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(924): Module 'C_REG_FD_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(985): Module 'C_GATE_BIT_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(1017): Module 'C_SHIFT_FD_V7_0' is not defined.
# ** Error: D:/Xilinx92i/practice02/mydds.v(1065): Module 'C_REG_FD_V7_0' is not defined.
# Optimization failed
# Error loading design
不懂了，这个要怎么改啊？还是没加库什么的加的少了，还是错了？