我认为他在起始位就进行了采样，不知道哪里表示他跳过了起始位的低电平，求各位老前辈赐教
以下是代码
波特率模块
1 module speed_select (
2 clk, rst_n ,
3 bps_start , clk_bps
4 );
5
6 input clk; // 50MHz
7 input rst_n ; //
8 input bps_start ; //
9 output clk_bps ; // clk_bps
10
11 /*
12 parameter bps9600 = 5207, // 9600bps
13 bps19200 = 2603, // 19200bps
14 bps38400 = 1301, // 38400bps
15 bps57600 = 867, // 57600bps
16 bps115200 = 433; // 115200bps
17
18 parameter bps9600_2 = 2603,
19 bps19200_2 = 1301,
20 bps38400_2 = 650,
21 bps57600_2 = 433,
22 bps115200_2 = 216;
23 */
24
25 //
26 `define BPS_PARA 5207 // 9600
27 `define BPS_PARA_2 2603 // 9600
28
29 reg[ 12 : 0] cnt ; //
30 reg clk_bps_r ; //
31
32 //---------------------------------------------------------
33 reg[ 2 : 0] uart_ctrl ; // uart
34 //---------------------------------------------------------
35
36 always @ ( posedge clk or negedge rst_n )
37 if(! rst_n ) cnt <= 13'd0 ;
38 else if(( cnt == `BPS_PARA ) || ! bps_start ) cnt <= 13'd0 ;
39 else cnt <= cnt+1'b1 ; //
40
41 always @ ( posedge clk or negedge rst_n )
42 if(! rst_n ) clk_bps_r <= 1'b0 ;
43 else if( cnt == `BPS_PARA_2 ) clk_bps_r <= 1'b1 ;
//clk_bps_r ,
44 else clk_bps_r <= 1'b0 ;
45
46 assign clk_bps = clk_bps_r ;
47
48 endmodule
接收模块
1 module my_uart_rx (
2 clk, rst_n ,
3 rs232_rx , rx_data , rx_int ,
4 clk_bps , bps_start
5 );
6
7 input clk; // 50MHz
8 input rst_n ; //
9 input rs232_rx ; // RS232
10 input clk_bps ; // clk_bps
11 output bps_start ; //
12 output [ 7: 0] rx_data ; //
13 output rx_int ; // ,
14
15 //---------------------------------------------------------
16 reg rs232_rx0 , rs232_rx1 , rs232_rx2 , rs232_rx3 ; //
17 wire neg_rs232_rx ; //
18
19 always @ ( posedge clk or negedge rst_n ) begin
20 if(! rst_n ) begin
21 rs232_rx0 <= 1'b0 ;
22 rs232_rx1 <= 1'b0 ;
23 rs232_rx2 <= 1'b0 ;
24 rs232_rx3 <= 1'b0 ;
25 end
26 else begin
27 rs232_rx0 <= rs232_rx ;
28 rs232_rx1 <= rs232_rx0 ;
29 rs232_rx2 <= rs232_rx1 ;
30 rs232_rx3 <= rs232_rx2 ;
31 end
32 end
33 // <20ns-40ns ( )
34 //
35 // 40ns
36 assign neg_rs232_rx = rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0; // neg_rs232_rx
37
38 //---------------------------------------------------------
39 reg bps_start_r ;
40 reg[ 3: 0] num; //
41 reg rx_int ; // ,
42
43 always @ ( posedge clk or negedge rst_n )
44 if(! rst_n ) begin
45 bps_start_r <= 1'bz ;
46 rx_int <= 1'b0 ;
47 end
48 else if( neg_rs232_rx ) begin
// rs232_rx
49 bps_start_r <= 1'b1 ; //
50 rx_int <= 1'b1 ; //
51 end
52 else if( num==4'd12 ) begin //
53 bps_start_r <= 1'b0 ; //
54 rx_int <= 1'b0 ; //
55 end
56
57 assign bps_start = bps_start_r ;
58
59 //---------------------------------------------------------
60 reg[ 7 : 0] rx_data_r ; //
61 //---------------------------------------------------------
62
63 reg[ 7 : 0] rx_temp_data ; //
64
65 always @ ( posedge clk or negedge rst_n )
66 if(! rst_n ) begin
67 rx_temp_data <= 8'd0 ;
68 num <= 4'd0 ;
69 rx_data_r <= 8'd0 ;
70 end
71 else if( rx_int ) begin //
72 if( clk_bps ) begin
// , 8bit 1 2
73 num <= num+1'b1 ;
74 case ( num)
75 4'd1:rx_temp_data[0] <= rs232_rx; // 0bit
76 4'd2:rx_temp_data [1] <= rs232_rx; // 1bit
77 4'd3:rx_temp_data [2] <= rs232_rx; // 2bit
78 4'd4:rx_temp_data [3] <= rs232_rx; // 3bit
79 4'd5:rx_temp_data [4] <= rs232_rx; // 4bit
80 4'd6:rx_temp_data [5] <= rs232_rx; // 5bit
81 4'd7:rx_temp_data [6] <= rs232_rx; // 6bit
82 4'd8:rx_temp_data [7] <= rs232_rx; // 7bit
83 default : ;
84 endcase
85 end
86 else if( num == 4'd12 ) begin
// 1+8+1(2)=11bit
87 num <= 4'd0 ; // STOP ,num
88 rx_data_r <= rx_temp_data ; // rx_data
89 end
90 end
91
92 assign rx_data = rx_data_r ;
93
94 endmodule
|
楼主
标题置顶
标题高亮
