module my_uart_tx(clk,rst_n,clk_bps,rx_data,rx_int,rs232_tx,bps_start);
input clk;
input rst_n;
input clk_bps;
//中间采样点
input[7:0] rx_data;
//接收寄存器
input rx_int;
//接收中断信号，接收期间为高电平
output rs232_tx;
//发送数据信号
output bps_start;
//波特率启动标志
//-----------------------------------
reg rx_int0,rx_int1,rx_int2;
wire neg_rs232_tx;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
rx_int0<=1'b0;
rx_int1<=1'b0;
rx_int2<=1'b0;
end
else begin
rx_int0<=rx_int;
rx_int1<=rx_int0;
rx_int2<=rx_int1;
end
assign neg_rs232_tx=rx_int2&(~rx_int1);
//------------------------------------
reg[7:0] tx_data;
//待发送数据的寄存器
//------------------------------------
reg bps_start_r;
reg tx_en;
//发送数据使能信号，高有效
reg[3:0] num;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
tx_data<=8'd0;
bps_start_r<=1'b0;
tx_en<=1'b0;
end
else if(neg_rx_int) begin
//接收数据完毕，准备把接收到的数据发回去
bps_start_r <= 1'b1;
tx_data <= rx_data;
//把接收到的数据存入发送数据寄存器
tx_en <= 1'b1;
//进入发送数据状态中
end
else if(num==4'd11) begin
bps_start_r<=1'b0;
tx_en<=1'b0;
end
assign bps_start=bps_start_r;
//-----------------------------------
reg rs232_tx_r;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
num <= 4'd0;
rs232_tx_r <= 1'b1;
end
else if(tx_en) begin
if(clk_bps)
begin
num<=num+1'b1;
case(num)
4'd0: rs232_tx_r<=1'b0;
4'd1: rs232_tx_r<=tx_data[0];
4'd2: rs232_tx_r<=tx_data[1];
4'd3: rs232_tx_r<=tx_data[2];
4'd4: rs232_tx_r<=tx_data[3];
4'd5: rs232_tx_r<=tx_data[4];
4'd6: rs232_tx_r<=tx_data[5];
4'd7: rs232_tx_r<=tx_data[6];
4'd8: rs232_tx_r<=tx_data[7];
4'd9: rs232_tx_r<=1'b1;
default: rs232_tx_r <= 1'b1;
endcase
end
else if(num==4'd11)
num<=4'd0;
end
assign rs232_tx = rs232_tx_r;
endmodule
怎么提示这个呢Error (10170): Verilog HDL syntax error at my_uart_tx.v(87) near text "endmodule"; expecting "end" |
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