本帖最后由 yejingang 于 2011-10-19 14:32 编辑
1.1 Features
High Performance 8051 μC Core
● Instruction set compatible with standard 8051
● High performance processor architecture that executes instructions in one to eight clocks, speed up to 33 MHz
Memory
● 64/4K bytes of program flash with In-System Programming (ISP) capability
● 0/60K bytes of program flash with In-Application Programming (IAP) and ISP capability
● 1280 bytes of data RAM
- 256 bytes internal RAM
- 1K bytes auxiliary RAM (AUXRAM)
● FLASH memory with security protection
● Hardware In-System Programming (ISP) without boot code
Digital Peripherals
● Five 8-bit I/O ports
- Configurable I/O with quasi-bidirectional, input, push-pull, and open-drain modes
- 5 V tolerant I/O
● Three 16-bit timers/counters (Timer0/1/2)
● Full-duplex serial port (UART)
● Single Master and Slave I2C interface for external device communication
● 4-channel Programmable Counter Array (PCA) with PWM, Capture and Compare functions
● Master/Slave Serial Peripheral Interface (SPI)
● Two external interrupts
● Programmable Watchdog Timer (WDT)
● One 16-bit timer (Timer3) support 3 capture inputs capability for hall sensor feedback
● Four independent 16-bit PWM duty control units with maximum 8 port pins:
- Six PWM output channels with mask control for BLDC application
- Three pairs complementary PWM with programmable dead-time insertion
- Independent polarity setting for each channel |
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