● Instruction set compatible with standard 8051
● High performance processor architecture that executes instructions in one to eight clocks, speed up to 33 MHz
Memory
● 64/4K bytes of program flash with In-System Programming (ISP) capability
● 0/60K bytes of program flash with In-Application Programming (IAP) and ISP capability
● 1280 bytes of data RAM
- 256 bytes internal RAM
- 1K bytes auxiliary RAM (AUXRAM)
● FLASH memory with security protection
● Hardware In-System Programming (ISP) without boot code
Digital Peripherals
● Five 8-bit I/O ports
- Configurable I/O with quasi-bidirectional, input, push-pull, and open-drain modes
- 5 V tolerant I/O
● Three 16-bit timers/counters (Timer0/1/2)
● Full-duplex serial port (UART)
● Single Master and Slave I2C interface for external device communication
● 4-channel Programmable Counter Array (PCA) with PWM, Capture and Compare polarity setting for each channel |
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