兄弟,还是不行啊
parameter CHANNEL = 396;
reg [CHANNEL-1:0] pwm_cs;
54:pwm_cs <= {(CHANNEL-1){1'b0},1'b1;
65:pwm_cs <= {CHANNEL){1'b0}};
ERROR:HDLCompiler:806 - "E:/FPGA/PWM/PWM_SETxn.v" Line 54: Syntax error near ",".
ERROR:HDLCompiler:806 - "E:/FPGA/PWM/PWM_SETxn.v" Line 65: Syntax error near ")".
ERROR:ProjectMgmt:497 - 2 error(s) found while parsing design hierarchy.
ERROR:HDLCompiler:806 - "E:/FPGA/PWM/PWM_SETxn.v" Line 54: Syntax error near ",".
ERROR:HDLCompiler:806 - "E:/FPGA/PWM/PWM_SETxn.v" Line 65: Syntax error near ")".
ERROR:ProjectMgmt:497 - 2 error(s) found while parsing design hierarchy.
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