library ieee;
use ieee.std_logic_1164.all;
ENTITY MUX21 IS
PORT(A,B,S:IN std_logic; Y:OUT std_logic);
END MUX21;
ARCHITECTURE one OF MUX21 IS
signal a1,b1,c1:std_logic;
begin
a1<=A and S;
b1<=not b;
c1<=(not S) and (not b1);
Y<=a1 or c1;
END architecture one;
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