用uart串口发送16位数据总是不对，调了一天了，求大佬帮助

只看该作者 · 2019-6-14 17:07

设置的16位数据是01000010 01000010，2个8位的10进制都是66，对应ascii是B，用串口调试工具显示接受了2个字符，但是只显示一个B
然后又用labwindows试验，收到的数据显示是66和-2，实在不知道哪里有问题
我把16位数据一起发送了，是按照uart协议发的，大佬们能看下吗

always@(posedge clk or negedge rst)
begin
  if(!rst)
   begin
      num<=0;
   tx_r<=1'b1;
   end
  else if(tx_en) begin
      if(clk_bps) begin
      num<=num+1;
   case(num)
      4'd0:tx_r<=1'b0;
   4'd1:tx_r<=tx_data[0];
   4'd2:tx_r<=tx_data[1];
   4'd3:tx_r<=tx_data[2];
   4'd4:tx_r<=tx_data[3];
   4'd5:tx_r<=tx_data[4];
   4'd6:tx_r<=tx_data[5];
   4'd7:tx_r<=tx_data[6];
   4'd8:tx_r<=tx_data[7];
   4'd9:tx_r<=1'b1;
   4'd14:tx_r<=1'b0;
   4'd15:tx_r<=tx_data[8];
   4'd16:tx_r<=tx_data[9];
   4'd17:tx_r<=tx_data[10];
   4'd18:tx_r<=tx_data[11];
   4'd19:tx_r<=tx_data[12];
   4'd20:tx_r<=tx_data[13];
   4'd21:tx_r<=tx_data[14];
   4'd22:tx_r<=tx_data[15];
   4'd23:tx_r<=1'b1;
   default:tx_r<=1'b1;
   endcase
end
else if(num==24)
      num<=0;
end
end

2万 · 2019-6-17 22:38

module uart_tx(
input clk,
input rst,
input [7:0] tx_data,
input tx_en,
output tx_rb,
output tx
);

reg    tx_rb,tx;
reg    send;
reg    wrsigbuf,wrsigrise;
reg    presult;
reg [7:0]cnt;
parameter paritymode = 1'b0;

always@(posedge clk or negedge rst)
      begin
         if(!rst)
            begin
                  wrsigbuf <= 0;
                  wrsigrise <= 0;
            end
         else
            begin
                  wrsigbuf <= tx_en;
                  wrsigrise <= (~wrsigbuf) & tx_en;
            end
      end

always@(posedge clk or negedge rst)
      begin
         if(!rst)
            begin
                  send <= 0;
            end
         else
            begin
                  if(wrsigrise && (~tx_rb))
                     begin
                        send <= 1;
                     end
                  else if(cnt == 8'd168)
                     begin
                        send <= 0;
                     end
            end
      end

always@(posedge clk or negedge rst)
      begin
         if(!rst)
            begin
                  cnt <= 0;
                  tx <= 1;
                  tx_rb <= 0;
            end
         else
            begin
                  if(send == 1)
                     begin
                        case(cnt)
                              8'd0:
                                 begin
                                    tx <= 0;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd16:
                                 begin
                                    tx <= tx_data[0];
                                    presult <= tx_data[0] ^ paritymode;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd32:
                                 begin
                                    tx <= tx_data[1];
                                    presult <= tx_data[1] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd48:
                                 begin
                                    tx <= tx_data[2];
                                    presult <= tx_data[2] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd64:
                                 begin
                                    tx <= tx_data[3];
                                    presult <= tx_data[3] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd80:
                                 begin
                                    tx <= tx_data[4];
                                    presult <= tx_data[4] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd96:
                                 begin
                                    tx <= tx_data[5];
                                    presult <= tx_data[5] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd112:
                                 begin
                                    tx <= tx_data[6];
                                    presult <= tx_data[6] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd128:
                                 begin
                                    tx <= tx_data[7];
                                    presult <= tx_data[7] ^ presult;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd144:
                                 begin
                                    tx <= presult;
                                    presult <= tx_data[0] ^ paritymode;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd160:
                                 begin
                                    tx <= 1;
                                    tx_rb <= 1;
                                    cnt <= cnt + 1;
                                 end
                              8'd168:
                                 begin
                                    tx <= 1;
                                    tx_rb <= 0;
                                    cnt <= cnt + 1;
                                 end
                              default:
                                 begin
                                    cnt <= cnt + 1;
                                 end
                        endcase
                     end
                  else
                     begin
                        tx <= 1;
                        cnt <= 0;
                        tx_rb <= 0;
                     end
            end
      end

endmodule

2万 · 2019-6-17 22:38

我用过的可以正常通信

用uart串口发送16位数据总是不对，调了一天了，求大佬帮助

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