module uart_tx(
input clk,
input rst,
input [7:0] tx_data,
input tx_en,
output tx_rb,
output tx
);
reg tx_rb,tx;
reg send;
reg wrsigbuf,wrsigrise;
reg presult;
reg [7:0]cnt;
parameter paritymode = 1'b0;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
wrsigbuf <= 0;
wrsigrise <= 0;
end
else
begin
wrsigbuf <= tx_en;
wrsigrise <= (~wrsigbuf) & tx_en;
end
end
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
send <= 0;
end
else
begin
if(wrsigrise && (~tx_rb))
begin
send <= 1;
end
else if(cnt == 8'd168)
begin
send <= 0;
end
end
end
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
cnt <= 0;
tx <= 1;
tx_rb <= 0;
end
else
begin
if(send == 1)
begin
case(cnt)
8'd0:
begin
tx <= 0;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd16:
begin
tx <= tx_data[0];
presult <= tx_data[0] ^ paritymode;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd32:
begin
tx <= tx_data[1];
presult <= tx_data[1] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd48:
begin
tx <= tx_data[2];
presult <= tx_data[2] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd64:
begin
tx <= tx_data[3];
presult <= tx_data[3] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd80:
begin
tx <= tx_data[4];
presult <= tx_data[4] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd96:
begin
tx <= tx_data[5];
presult <= tx_data[5] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd112:
begin
tx <= tx_data[6];
presult <= tx_data[6] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd128:
begin
tx <= tx_data[7];
presult <= tx_data[7] ^ presult;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd144:
begin
tx <= presult;
presult <= tx_data[0] ^ paritymode;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd160:
begin
tx <= 1;
tx_rb <= 1;
cnt <= cnt + 1;
end
8'd168:
begin
tx <= 1;
tx_rb <= 0;
cnt <= cnt + 1;
end
default:
begin
cnt <= cnt + 1;
end
endcase
end
else
begin
tx <= 1;
cnt <= 0;
tx_rb <= 0;
end
end
end
endmodule
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