第一个verilog的LED程序，仿真成功

1万 · 2019-7-2 11:26

本帖最后由 springvirus 于 2019-7-2 11:30 编辑

因为偶的板子是Cyclone系列的片子，实在太老，所以用的quartus II 9.1
先感受下verilog结构和仿真操作，改天烧到俺的板子试试
仿真要修改下程序里计数器的最大值，实际在板子上跑时，再改回实际所需的值，比如这里流水灯的200ms间隔

module FPGA_EP1C6Q240_led (

      input sys_clk,
      input sys_rst_n,

      output reg [3:0] led,

      //7 seg shumaguan  segment select
      output reg [7:0] seg_sel,

      //7 seg shumaguan  bit  select
      output reg [1:0] bit_sel

);

reg [23:0] counter;
reg [7:0] magic_liushui_counter;

always @(posedge sys_clk or negedge sys_rst_n)
begin
      if(!sys_rst_n)
            begin
                     counter <= 24'd0;
                     magic_liushui_counter <= 8'd0;
            end
      //else if(counter < 24'd1000_0000)
      else if(counter < 24'd4)
            counter <= counter + 24'd1;
      //else if(counter == 24'd1000_0000)
      else if(counter == 24'd4)
            begin
                     counter <= 24'd0;

                     if(magic_liushui_counter < 8'd7)
                              magic_liushui_counter <= magic_liushui_counter + 8'd1;
                     else if(magic_liushui_counter == 8'd7)
                              magic_liushui_counter <= 8'd0;

            end
end

//high level turn on the led, low level turn off the led
//when counter == 24'd1000_0000, level 1 left shift,
//[3:0] = 0001 -> [3:0] = 0010 -> [3:0] = 0100 -> [3:0] = 1000
always @(posedge sys_clk or negedge sys_rst_n)
begin
      if(!sys_rst_n)
            begin
                     led <= 4'b0001;
                     //when power on, sgsel0 and sgsel1 are valid both.
                     bit_sel <= 2'b11;
            end
      //else if(counter == 24'd1000_0000)
      else if(counter == 24'd4)
            begin
                     led[3:0] <= {led[2:0], led[3]};


                     if(magic_liushui_counter == 8'd0)
                              //seg a is on
                              seg_sel <= 8'b0000_0001;
                     else if(magic_liushui_counter == 8'd1)
                              //seg b is on
                              seg_sel <= 8'b0000_0010;
                     else if(magic_liushui_counter == 8'd2)
                              //seg g is on
                              seg_sel <= 8'b0100_0000;
                     else if(magic_liushui_counter == 8'd3)
                              //seg e is on
                              seg_sel <= 8'b0001_0000;
                     else if(magic_liushui_counter == 8'd4)
                              //seg d is on
                              seg_sel <= 8'b0000_1000;
                     else if(magic_liushui_counter == 8'd5)
                              //seg c is on
                              seg_sel <= 8'b0000_0100;
                     else if(magic_liushui_counter == 8'd6)
                              //seg g is on
                              seg_sel <= 8'b0100_0000;
                     else if(magic_liushui_counter == 8'd7)
                              //seg f is on
                              seg_sel <= 8'b0010_0000;


            end
      else

            led <= led;

end

endmodule

1万 · 2019-7-2 11:28

参考了原子哥的代码

实际跑程序时，需要的激励模块
module main_test_flow_led();

//f = 50MHz T = 20ns
parameter T = 20;

reg main_sys_clk;

reg main_sys_rst_n;

//answer: use pin planner in quartus II to assign pins.
wire [3:0] main_led;

wire [7:0] main_seg_sel;

wire [1:0] main_bit_sel;

initial
begin
main_sys_clk <= 1'b0;
main_sys_rst_n <= 1'b0;

//when power on, after 20ns, sys_rst_n pull high
# T main_sys_rst_n <= 1'b1;

end

//every 10ns , sys_clk toggle
always # (T/2) main_sys_clk <= ~main_sys_clk;

//in module main_led, make FPGA_EP1C6Q240 shilihua
//
FPGA_EP1C6Q240_led u0_flow_led (

.sys_clk(main_sys_clk),
.sys_rst_n(main_sys_rst_n),
.led(main_led),
.seg_sel(main_seg_sel),
.bit_sel(main_bit_sel)
);

endmodule

2万 · 2019-7-2 23:13

FPGA是有些难度尤其是到后期严谨的时序上

1万 · 2019-7-3 10:37

zhangmangui 发表于 2019-7-2 23:13
FPGA是有些难度尤其是到后期严谨的时序上

在面包板社区，看到小梅哥的一系列博文，时序方面的

感觉写的不错

https://www.mianbaoban.cn/search.php?mod=blog&searchid=14&searchsubmit=yes&kw=%E5%B0%8F%E6%A2%85%E5%93%A5FPGA%E6%97%B6%E5%BA%8F%E5%88%86%E6%9E%90%E7%AC%94%E8%AE%B0