行为建模时序逻辑电路:
module and_gate1(clk, a, b, s);
input clk;
input a;
input b;
output reg s;
//行为建模时序逻辑电路(二输入与门)
always @ (posedge clk) //上升沿触发
begin
s <= a & b;
end
endmodule
行为建模组合逻辑电路:
module and_gate2(a, b, s);
input a; //输入信号a
input b; //输入信号b
output reg s; //输出信号c
//行为建模组合逻辑电路(二输入与门)
always @ (*) //条件;*代表自动寻找所对应的电平值 电平值触发
begin
s = a & b;
end
endmodule |