源代码：
module and_gate1(clk, a, b, s);
input clk;
input a;
input b;
output reg s;
//行为建模时序逻辑电路（二输入与门）
always @ (posedge clk) //上升沿触发
begin
s <= a & b;
end
endmodule
测试代码：
`timescale 1ns/1ps
module and_gate1_tb;
reg clk;
reg a;
reg b;
wire s;
and_gate1 and_gate1a(
.clk(clk),
.a(a),
.b(b),
.s(s)
);
initial
begin
clk = 0;
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
#100 $stop;
end
always #10 clk = ~clk;
endmodule |
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