时钟频率的规划工具

/****************************************************************************

 * [url=home.php?mod=space&uid=288409]@file[/url]     1.c

 * [url=home.php?mod=space&uid=895143]@version[/url]  V1.03

 * [url=home.php?mod=space&uid=212281]@date[/url]     2019/08/18-12:56:20

 * [url=home.php?mod=space&uid=247401]@brief[/url]    NuMicro generated code file

 *

 * Copyright (C) 2013-2019 Nuvoton Technology Corp. All rights reserved.

*****************************************************************************/



/********************

MCU:M4TKLE6AE(LQFP48)

Base Clocks:

Enabled-Module Frequencies:

FMCIDLE=Bus Clock(HCLK):Disabled/Engine Clock:

ISP=Bus Clock(HCLK):Disabled/Engine Clock:

WDT=Bus Clock(PCLK):Disabled/Engine Clock:

WWDT=Bus Clock(PCLK):Disabled/Engine Clock:

********************/



#include "M451Series.h"

/*----------------------------------------------------------------------------

  Define HXT clock.

  Please locate and modify the real one in your project.

  Otherwise, the project may fail to build.

 *----------------------------------------------------------------------------*/

#define __HXT         (0UL)  /*!< High Speed External Crystal Clock Frequency */



/*

 * @brief This function updates clock registers to fulfil the configuration

 * @param None

 * [url=home.php?mod=space&uid=266161]@return[/url] None

 */

void SYS_Init()

{

    /*---------------------------------------------------------------------------------------------------------*/

    /* Init System Clock                                                                                       */

    /*---------------------------------------------------------------------------------------------------------*/

    //CLK->PWRCTL = (CLK->PWRCTL & ~(0x0000000Ful)) | 0x0000001Ful;

    //CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFul)) | 0x0005C02Eul;

    //CLK->CLKDIV0 = (CLK->CLKDIV0 & ~(0x00FF0FFFul)) | 0x00000000ul;

    //CLK->CLKDIV1 = (CLK->CLKDIV1 & ~(0x000000FFul)) | 0x00000000ul;

    //CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(0x000000FFul)) | 0x0000003Ful;

    //CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(0xF3777703ul)) | 0xB377770Ful;

    //CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(0x000000FFul)) | 0x000000ABul;

    //CLK->CLKSEL3 = (CLK->CLKSEL3 & ~(0x00000203ul)) | 0x00000003ul;

    //CLK->AHBCLK = (CLK->AHBCLK & ~(0x0000809Eul)) | 0x00008004ul;

    //CLK->APBCLK0 = (CLK->APBCLK0 & ~(0x1D0F73FFul)) | 0x00000001ul;

    //CLK->APBCLK1 = (CLK->APBCLK1 & ~(0x02031001ul)) | 0x00000000ul;

    //CLK->CLKOCTL = (CLK->CLKOCTL & ~(0x0000007Ful)) | 0x00000000ul;

    //SysTick->CTRL = (SysTick->CTRL & ~(0x00000005ul)) | 0x00000000ul;



    /* Unlock protected registers */

    SYS_UnlockReg();



    /* Enable clock source */

    CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk|CLK_PWRCTL_HIRCEN_Msk|CLK_PWRCTL_LXTEN_Msk|CLK_PWRCTL_HXTEN_Msk);



    /* Waiting for clock source ready */

    CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk|CLK_STATUS_HIRCSTB_Msk|CLK_STATUS_LXTSTB_Msk|CLK_STATUS_HXTSTB_Msk);



    /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */

    /* Set HCLK clock */

    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));



    /* Set PCLK-related clock */

    CLK->CLKSEL0 = CLK->CLKSEL0 & ~CLK_CLKSEL0_PCLK0SEL_Msk;

    CLK->CLKSEL0 = CLK->CLKSEL0 & ~CLK_CLKSEL0_PCLK1SEL_Msk;



    /* Enable IP clock */

    CLK_EnableModuleClock(FMCIDLE_MODULE);

    CLK_EnableModuleClock(ISP_MODULE);

    CLK_EnableModuleClock(WDT_MODULE);

    CLK_EnableModuleClock(WWDT_MODULE);



    /* Set IP clock */

    CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, MODULE_NoMsk);

    CLK_SetModuleClock(WWDT_MODULE, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048, MODULE_NoMsk);



    /* Update System Core Clock */

    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */

    SystemCoreClockUpdate();



    /* Lock protected registers */

    SYS_LockReg();



    return;

}



/*** (C) COPYRIGHT 2013-2019 Nuvoton Technology Corp. ***/