代码如下：clk为系统时钟20MHz，rst_n为系统复位，clk_num为输入控制输出时钟频率的输入变量，clk_out为输出时钟。
不知道是思路问题还是代码问题，始终不正确
//系统时钟20MHz，单位时间为50ns
`timescale 1ns / 1ps
module max7418
(
input clk,
input rst_n,
input clk_num,
output reg clk_out
);
reg[24:0] cnt;
reg[24:0] clk_cnt;
always @(clk_num)
begin
if(!rst_n)
begin
clk_cnt <= 25'd0;
end
else
begin
clk_cnt <= 20_000_000 / clk_num;
clk_cnt <= clk_cnt - 1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt <= 25'd0;
end
else if (cnt == clk_cnt)
begin
cnt <= 25'd0;
end
else
begin
cnt <= cnt + 1'd1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_out <= 0;
end
else if (cnt == clk_cnt)
begin
clk_out <= !clk_out;
end
end
endmodule |
|
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