module fifo_ctrol(
input user_clk,
input ddr_clk,
input rst,
);
reg [511:0] data_in;
reg wr_en;
reg rd_en;
wire [255:0] data_out;
wire full_flag;
wire empty_flag;
wire valid;
wire wr_ack;
wire [8:0] wr_data_count;
wire [9:0] rd_data_count;
always@(posedge user_clk or negedge rst)
begin
if(!rst)
begin
wr_en<=0;
data_in<=0;
end
else if(!full_flag)
begin
wr_en<=1;
if(wr_ack)
begin
data_in<=data_in+512'd10;
end
end
else
begin
wr_en<=0;
end
end
always@(posedge ddr_clk or negedge rst)
begin
if(!rst)
begin
rd_en<=0;
end
else if((!empty_flag))
begin
//data_out_r<=data_out;
rd_en<=1;
end
end
fifo_ip wr_fifo (
.rst(rst), // input rst
.wr_clk(user_clk), // input wr_clk
.rd_clk(ddr_clk), // input rd_clk
.din(data_in_wire), // input [511 : 0] din
.wr_en(wr_en_wire), // input wr_en
.rd_en(rd_en_wire), // input rd_en
.dout(data_out), // output [255 : 0] dout
.full(full_flag), // output full
.wr_ack(wr_ack), // output wr_ack
.empty(empty_flag), // output empty
.valid(valid), // output valid
.rd_data_count(rd_data_count), // output [9 : 0] rd_data_count
.wr_data_count(wr_data_count) // output [8 : 0] wr_data_count
);
endmodule
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