LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
LIBRARY LPM;
USE LPM.LPMCOMPONENTS.ALL;
ENTITY ddsc IS
GENERIC(
freq_width: INTEGER :=32;
phase_width : INTEGER :=12;
adder_width : INTEGER :=32;
romad_width : INTEGER :=10;
rom_d_width : INTEGER :=10
);
PORT(
clk : IN STD_LOGIC;
freqin : IN STD_LOGIC_VECTOR(freq_width-1 DOWNTO 0) ;
ddsout : OUT STD_LOGIC_VECTOR(rom_d_width-1 DOWNTO 0));
END ENTITY ddsc;
ARCHITECTURE behave OF ddsc IS
SIGNAL acc:STD_LOGIC_VECTOR(adder_width-1 DOWNTO 0);
SIGNAL romaddr :STD_LOGIC_VECTOR(romad_width-1 DOWNTO 0) ;
BEGIN
process (clk)
BEGIN
IF (clk'event and clk ='1') THEN
acc<=acc+freqin;
END IF;
END PROCESS;
romaddr<=acc(phase_width-1 downto phase_width-romad_width) ;
i_rom :lpm_rom
GENERIC MAP (
Lpm_width=>rom_d_width,
Lpm_widthad=>romad_width,
Lpm_addreaa_control=>"NREGISTERED",
Lpm_outdata=>"EGISTERED",
Lpm_file=>"sin_rom.mif")
PORT MAP(
outclock=>clk,
ddress=>romaddr,
q=>ddsout);
END ARCHITECTURE behave;
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