#pragma config BWRP = OFF // Table Write Protect Boot (Boot segment may be written)
#pragma config BSS = OFF // Boot segment Protect (No boot program Flash segment)
// FGS
#pragma config GWRP = OFF // General Segment Code Flash Write Protection bit (General segment may be written)
#pragma config GCP = OFF // General Segment Code Flash Code Protection bit (No protection)
// FOSCSEL
#pragma config FNOSC = FRCDIV // Oscillator Select (8 MHz FRC oscillator with divide-by-N (FRCDIV))
#pragma config IESO = ON // Internal External Switch Over bit (Internal External Switchover mode disabled (Two-Speed Start-up disabled))
// FOSC
#pragma config POSCMOD = NONE // Primary Oscillator Configuration bits (Primary oscillator disabled)
#pragma config OSCIOFNC = ON // CLKO Enable Configuration bit (CLKO output disabled; pin functions as port I/O)
#pragma config POSCFREQ = HS // Primary Oscillator Frequency Range Configuration bits (Primary oscillator/external clock input frequency greater than 8 MHz)
#pragma config SOSCSEL = SOSCHP // SOSC Power Selection Configuration bits (Secondary oscillator configured for high-power operation)
#pragma config FCKSM = CSECMD // Clock Switching and Monitor Selection (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
// FWDT
#pragma config WDTPS = PS256 // Watchdog Timer Postscale Select bits (1:256)
#pragma config FWPSA = PR128 // WDT Prescaler (WDT prescaler ratio of 1:128)
#pragma config WINDIS = OFF // Windowed Watchdog Timer Disable bit (Standard WDT selected; windowed WDT disabled)
#pragma config FWDTEN = OFF // Watchdog Timer Enable bit (WDT enabled)
// FPOR
#pragma config BOREN = BOR3 // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware; SBOREN bit disabled)
#pragma config PWRTEN = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config I2C1SEL = PRI // Alternate I2C1 Pin Mapping bit (Default location for SCL1/SDA1 pins)
#pragma config BORV = V18 // Brown-out Reset Voltage bits (Brown-out Reset set to lowest voltage (1.8V))
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RA5 input pin disabled)
// FICD
#pragma config ICS = PGx1 // ICD Pin Placement Select bits (PGC1/PGD1 are used for programming and debugging the device)
// FDS
#pragma config DSWDTPS = DSWDTPS8 // Deep Sleep Watchdog Timer Postscale Select bits (1:131,072 (135 Seconds))
#pragma config DSWDTOSC = SOSC // DSWDT Reference Clock Select bit (DSWDT uses SOSC as reference clock)
#pragma config RTCOSC = SOSC // RTCC Reference Clock Select bit (RTCC uses SOSC as reference clock)
#pragma config DSBOREN = ON // Deep Sleep Zero-Power BOR Enable bit (Deep Sleep BOR enabled in Deep Sleep)
#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable bit (DSWDT enabled)
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