TI 公司的DM355是高度集成可编程平台,适用于数码相机,数码相框,IP安全照相机,4路数字视频摄影机,视频门铃应用和其它低成本手提视频应用. DM355处理器核是ARM926EJ-S RISC处理器,集成了高性能的MPEG4 HD (720p)编译码器(CODEC)和JPEG编译码器(CODEC),高达5000万象素/秒. DM355具有高质量,低功耗和非常低的价格.本文介绍了DM355达标主要特性,方框图, 采用TMS320DM3x的IP 照相机参考设计软件框图以及DM355IPNC-TC922, DM355IPNC-VCA1和DM355IPNC-MT5 IP 照相机参考设计方框图.
The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality,
and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.
The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core incorporates:
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.
The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.
The DM355 peripheral set includes:
An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit imers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
A high speed synchronous memory interface for DDR2/mDDR.
Features
Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation.
High-Performance Digital Media System-on-Chip
135-, 216-MHz ARM926EJ-S Clock Rate
Fully Software-Compatible With ARM9
Extended Temperature support for 135- and 216-Mhz Devices are Available
ARM926EJ-S Core
Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
DSP Instruction Extensions and Single Cycle MAC
ARM Jazelle Technology
EmbeddedICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
16K-Byte Instruction Cache
8K-Byte Data Cache
32K-Byte RAM
8K-Byte ROM
Little Endian
MPEG4/JPEG Coprocessor
Fixed Function Coprocessor Supports:
MPEG4 SP Codec at HD (720p), D1, VGA, SIF
JPEG Codec up to 50M Pixels per Second
Video Processing Subsystem
Front End Provides:
Hardware IPIPE for Real-Time Processing
up to 14-bit CCD/CMOS Digital Interface
16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
10-/8-bit CCIR6565/BT655 Interface
Up to 75-MHz Pixel Clock
Histogram Module
Resize Engine
Resize Images From 1/16x to 8x
Separate Horizontal/Vertical Control
Two Simultaneous Output Paths
Back End Provides:
Hardware On-Screen Display (OSD)
Composite NTSC/PAL video encoder output
8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
Supports digital HDTV (720p/1080i) output for connection to external encoder
External Memory Interfaces (EMIFs)
DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
Asynchronous16-/8-bit Wide EMIF (AEMIF)
Flash Memory Interfaces
NAND (8-/16-bit Wide Data)
OneNAND(16-bit Wide Data)
Flash Card Interfaces
Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
SmartMedia
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
USB 2.0 Full and High-Speed Device
USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and CTS Flow Control)
Three Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I2C) Bus
Two Audio Serial Port (ASP)
I2S and TDM I2S
AC97 Audio Codec Interface
S/PDIF via Software
Standard Voice Codec Interface (AIC12)
SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
Device Revision ID Readable by ARM
337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
3.3-V and 1.8-V I/O, 1.3-V Internal
图1.DM355功能方框图
图2.采用TMS320DM3x的IP 照相机参考设计软件框图
图3.DM365IPNC-MT5 IP照相机外形图
Wide Dynamic Range (WDR) IP Camera Reference Design:
Hardware features
TMS320DM355 SoC, ARM926 and hardware video coprocessor
TC922 TI’s WDR CMOS imager optimized for high-light/low-light performance
Board size 65×50 mm
Low power (< 3 W)
Software features
Complete Linux-based IP network camera application including free source code
Dual-stream capabilities
– MPEG-4 SVGA+ MJPEG VGA + G.711
Triple-stream capabilities
MPEG-4 SVGA + MJPEG VGA + MPEG-4 QVGA + G.711
MPEG-4 VGA + MJPEG VGA + MPEG-4 QVGA + G.711
Integrated auto white balance and auto exposure
Field-proven, robust, royalty-free bundled MPEG-4 and MJPEG video codecs
DaVinci IP camera software framework including I/O APIs, media APIs and DaVinci Codec Engine
Ability to add video analytics with DaVinci TMS320DM643x digital media processors
图4.WDR DM355 IP 照相机参考设计方框图: DM355IPNC-TC922
Video Content Analysis (VCA) DM355 IP Camera Reference Design: DM355IPNC-VCA1
Hardware features
DaVinci TMS320DM6435 digital media processor
DaVinci TMS320DM355 SoC, ARM926 and hardware video coprocessor
Aptina 5 MP sensor (2×2 binning ~1.3 MP)
VCA daughter board size 41×40 mm
Software features
Complete Linux-based IP network camera application including free source code
Dual-stream capabilities
MPEG-4 HD 720P + MPEG-4 CIF + G.711
Triple-stream capabilities
MPEG-4 HD 720P + MJPEG VGA + MJPEG CIF + G.711
Integrated auto white balance and auto exposure
Field-proven, robust, royalty-free bundled MPEG-4 and MJPEG video codecs
DaVinci IP camera software framework including I/O APIs, media APIs and DaVinci Codec Engine
图5.VCA DM355 IP照相机参考设计方框图: DM355IPNC-VCA1
TMS320DM355 IP Camera Reference Design: DM355IPNC-MT5
Hardware features
TMS320DM355 SoC, ARM926 and hardware video coprocessor
Aptina 5 MP sensor (2×2 binning ~1.3 MP) CMOS imager optimized for low-light performance
Board size 65×50 mm
Low power (< 3 W)
Software features
Complete Linux-based IP camera application including free source code
Dual-stream capabilities
MPEG-4 HD 720p + MPEG-4 CIF + G.711
MPEG-4 HD 720p + MJPEG CIF + G.711
Integrated auto white balance and auto exposure
Field-proven, robust, royalty-free bundled MPEG-4 and MJPEG video codecs
DaVinci IP camera software framework including I/O APIs, media APIs and DaVinci Codec Engine
Ability to add video analytics with DaVinci TMS320DM643x digital media processors
图6. DM355 IP 照相机参考设计方框图: DM355IPNC-MT5 |
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