本帖最后由 Cjy_JDxy 于 2020-3-27 17:33 编辑
今天捣鼓了一下汇编驱动LED。
代码：
#include "p18f47q10.inc"
; CONFIG1L
CONFIG FEXTOSC = XT ; External Oscillator mode Selection bits (XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power)
CONFIG RSTOSC = EXTOSC ; Power-up default value for COSC bits (EXTOSC operating per FEXTOSC bits (device manufacturing default))
; CONFIG1H
CONFIG CLKOUTEN = OFF ; Clock Out Enable bit (CLKOUT function is disabled)
CONFIG CSWEN = ON ; Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
CONFIG FCMEN = ON ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
; CONFIG2L
CONFIG MCLRE = EXTMCLR ; Master Clear Enable bit (MCLR pin (RE3) is MCLR)
CONFIG PWRTE = OFF ; Power-up Timer Enable bit (Power up timer disabled)
CONFIG LPBOREN = OFF ; Low-power BOR enable bit (Low power BOR is disabled)
CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)
; CONFIG2H
CONFIG BORV = VBOR_190 ; Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 1.90V)
CONFIG ZCD = OFF ; ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
CONFIG PPS1WAY = ON ; PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)
; CONFIG3L
CONFIG WDTCPS = WDTCPS_31 ; WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
CONFIG WDTE = OFF ; WDT operating mode (WDT Disabled)
; CONFIG3H
CONFIG WDTCWS = WDTCWS_7 ; WDT Window Select bits (window always open (100%); software control; keyed access not required)
CONFIG WDTCCS = SC ; WDT input clock selector (Software Control)
; CONFIG4L
CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
CONFIG WRT4 = OFF ; Write Protection Block 4 (Block 4 (010000-013FFFh) not write-protected)
CONFIG WRT5 = OFF ; Write Protection Block 5 (Block 5 (014000-017FFFh) not write-protected)
CONFIG WRT6 = OFF ; Write Protection Block 6 (Block 6 (018000-01BFFFh) not write-protected)
CONFIG WRT7 = OFF ; Write Protection Block 7 (Block 7 (01C000-01FFFFh) not write-protected)
; CONFIG4H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
CONFIG SCANE = ON ; Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)
CONFIG LVP = ON ; Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)
; CONFIG5L
CONFIG CP = OFF ; UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)
CONFIG CPD = OFF ; DataNVM Memory Code Protection bit (DataNVM code protection disabled)
; CONFIG5H
; CONFIG6L
CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR4 = OFF ; Table Read Protection Block 4 (Block 4 (010000-013FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR5 = OFF ; Table Read Protection Block 5 (Block 5 (014000-017FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR6 = OFF ; Table Read Protection Block 6 (Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR7 = OFF ; Table Read Protection Block 7 (Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks)
; CONFIG6H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
N1 EQU 20H
N2 EQU 21H
org 0000h
goto START
org 0030
START
nop
BANKSEL TRISE
MOVLW 0
MOVWF TRISE
MAIN
BANKSEL PORTE
MOVLW 0
MOVWF PORTE
CALL DELAY
MOVLW 1
MOVWF PORTE
CALL DELAY
GOTO MAIN
DELAY
BANKSEL N1
MOVLW 0xF0
MOVWF N1
DELAY1
MOVLW 0xF0
MOVWF N2
DELAY2
DECFSZ N2,1
GOTO DELAY2
DECFSZ N1,1
GOTO DELAY1
RETURN
end
效果图：
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