#define PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */
#define USART1TX_VECTOR (2 * 2u) /* 0xFFE4 USART 1 Transmit */
#define USART1RX_VECTOR (3 * 2u) /* 0xFFE6 USART 1 Receive */
#define PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */
#define ADC_VECTOR (7 * 2u) /* 0xFFEE ADC */
#define USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */
#define USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */
#define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watc×dog Timer */
#define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR (12 * 2u) /* 0xFFF8 Timer B CC1-6, TB */
#define TIMERB0_VECTOR (13 * 2u) /* 0xFFFA Timer B CC0 */
#define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maska××e */
#define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [×ig×est Priority] */
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