LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41A IS
PORT(A,B,C,D,S1,S2:IN STD_LOGIC;Y:OUTSTD_LOGIC)；
END ENTITY MUX41A;
ARCHITECTURE BHV OF MUX41A IS
SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=S1&S0;
PROCESS(S1,S0)BEGIN
CASE (S) IS
WHEN"00"=>Y<=A;
WHEN"01"=>Y<=B;
WHEN"10"=>Y<=C;
WHEN"11"=>Y<=D;
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END BHV; |
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