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[MCU] 用2块板子进行CAN通信

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 楼主| pengf 发表于 2020-5-29 23:23 | 显示全部楼层 |阅读模式
CAN, 通信, CAN通信, AN, can模块
一块发送一块接受，可以做到，认为CAN模块是好的。

然后我开始与CAN设备通信，1个邮箱发送一个邮箱接收，ID与协议设置的一致，波特率当然也一致，不然发送不了。
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hanwe 发表于 2020-5-29 23:26 | 显示全部楼层

楼主程序可以公开吗？贴程序看下吧，这么说看不出什么原因
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 楼主| pengf 发表于 2020-5-29 23:27 | 显示全部楼层
void main()
{
unsigned int kk, t;
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */

//   struct ECAN_REGS ECanaShadow;

   struct ECAN_REGS ECanbShadow;

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
   InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();  // Skipped for this example

   // Just initalize eCAN pins for this example
   // This function is in DSP2833x_ECan.c
//  InitECanGpio();
   InitECanbGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;


   InitPieVectTable();


  // InitECan();
  InitECanb();


/*
  ECanbMboxes.MBOX24.MSGID.all = 0x90200000; // Extended Identifier



  ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
   ECanbShadow.CANMD.bit.MD24 = 1;    ///  1： 接收邮箱  0：发送邮箱
   ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;



   ECanbShadow.CANME.all = ECanbRegs.CANME.all;
  ECanbShadow.CANME.bit.ME24 = 1;     ///  1：使能    0：  不使能
   ECanbRegs.CANME.all = ECanbShadow.CANME.all;


   ECanbMboxes.MBOX24.MSGCTRL.bit.DLC = 8;

    ECanbMboxes.MBOX24.MSGCTRL.bit.RTR = 0;

        */
        EALLOW;

//   ECanbRegs.CANGAM.all = 0x90200000;

//        ECanbLAMRegs.LAM24.all = 0x00000000;
    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

        ECanbRegs.CANMIM.all = 0xffffffff;

        ECanbRegs.CANMIL.all = 0;

        ECanbRegs.CANGIF0.all = 0xffffffff;

        ECanbRegs.CANGIM.bit.I0EN = 1;

        EDIS;


        PieCtrlRegs.PIEIER9.bit.INTx7 = 1;

        IER |= M_INT9;

        EINT;

        ERTM;

   j=0x01;

/* Begin transmitting */

while(1)
{
  // for(i=0; i < TXCOUNT; i++)
   {

   for(t = 0x00;t < 2;t++)
   {

       InitECanb();

   
       ECanbShadow.CANTRS.all = 0;
      ECanbShadow.CANTRS.bit.TRS25 = 1;             // Set TRS for mailbox under test
       ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all;
       kk = 0;
       do
            {
                 kk = kk + 1;

              ECanbShadow.CANTA.all = ECanbRegs.CANTA.all;
                } while((ECanbShadow.CANTA.bit.TA25 == 0 ) && (kk < 10000));   // Wait for TA5 bit to be set..

         if( kk < 10000) break;
      }  
          if(kk<10000) j++;

       ECanbShadow.CANTA.all = 0;
       ECanbShadow.CANTA.bit.TA25 = 1;                      // Clear TA5
       ECanbRegs.CANTA.all = ECanbShadow.CANTA.all;


     
    }
        }
    // asm(" ESTOP0");  // Stop here
}
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 楼主| pengf 发表于 2020-5-29 23:29 | 显示全部楼层
void InitECanb(void)                // Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanbShadow;

   EALLOW;                // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

        ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.SCB = 1;
        ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

   

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//        as a matter of precaution.

        ECanbRegs.CANTA.all        = 0xFFFFFFFF;        /* Clear all TAn bits */

        ECanbRegs.CANRMP.all = 0xFFFFFFFF;        /* Clear all RMPn bits */

        ECanbRegs.CANGIF0.all = 0xFFFFFFFF;        /* Clear all interrupt flag bits */
        ECanbRegs.CANGIF1.all = 0xFFFFFFFF;



        ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
        {
            ECanbShadow.CANES.all = ECanbRegs.CANES.all;
        } while(ECanbShadow.CANES.bit.CCE != 1 );                 // Wait for CCE bit to be  cleared..


    ECanbShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
        /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
           See Note at end of file */
                ECanbShadow.CANBTC.bit.BRPREG = 39;
                ECanbShadow.CANBTC.bit.TSEG2REG = 2;
                ECanbShadow.CANBTC.bit.TSEG1REG = 10;
        #endif
        #if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
        /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
           See Note at end of file */
            ECanbShadow.CANBTC.bit.BRPREG = 4;
                ECanbShadow.CANBTC.bit.TSEG2REG = 1;
                ECanbShadow.CANBTC.bit.TSEG1REG = 6;
        #endif

    ECanbShadow.CANBTC.bit.SAM = 1;
    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanbShadow.CANMC.bit.SUSP = 0 ;
    ECanbShadow.CANMC.bit.PDR = 0 ;
        ECanbShadow.CANMC.bit.DBO = 0 ;
        ECanbShadow.CANMC.bit.WUBA = 0 ;
        ECanbShadow.CANMC.bit.CDR = 0 ;
        ECanbShadow.CANMC.bit.ABO = 0 ;
        ECanbShadow.CANMC.bit.STM = 0 ;
        ECanbShadow.CANMC.bit.SRES = 0 ;
        ECanbShadow.CANMC.bit.MBNR = 0 ;

    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
        ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 0 );                 // Wait for CCE bit to be  cleared..


/* Disable all Mailboxes  */
        ECanbRegs.CANME.all = 0;                // Required before writing the MSGIDs

  //  EDIS;
          ECanbMboxes.MBOX25.MSGID.all = 0x90200000; // Extended Identifier

          ECanbMboxes.MBOX28.MSGID.all = 0x90200000;
/* Configure Mailbox under test as a Transmit mailbox */

   ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
   ECanbShadow.CANMD.bit.MD25 = 0;    ///  1： 接收邮箱  0：发送邮箱
   ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

   ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
   ECanbShadow.CANMD.bit.MD28 = 1;    ///  1： 接收邮箱  0：发送邮箱
   ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

/* Enable Mailbox under test */

   ECanbShadow.CANME.all = ECanbRegs.CANME.all;
   ECanbShadow.CANME.bit.ME25 = 1;     ///  1：使能    0：  不使能
   ECanbRegs.CANME.all = ECanbShadow.CANME.all;

     ECanbShadow.CANME.all = ECanbRegs.CANME.all;
  ECanbShadow.CANME.bit.ME28 = 1;     ///  1：使能    0：  不使能
   ECanbRegs.CANME.all = ECanbShadow.CANME.all;

/* Write to DLC field in Master Control reg */

   ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8;

   ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0;

    ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8;

    ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0;

/* Write to the mailbox RAM field */

   ECanbMboxes.MBOX25.MDL.all = 0x00000000;
   ECanbMboxes.MBOX25.MDH.all = 0x00610000;

    EDIS;
//  j=0x01;
}
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 楼主| pengf 发表于 2020-5-29 23:32 | 显示全部楼层
interrupt void ECAN0INTB_ISR(void)  // eCAN-B
{
             int z=0;
           while((ECanbRegs.CANRMP.all != 0x10000000 )&&(z<10000)) z++;
                  

                 ECanbRegs.CANRMP.all = 0x10000000;

                 datah = ECanbMboxes.MBOX28.MDH.all;

                 datal = ECanbMboxes.MBOX28.MDL.all;

                 PieCtrlRegs.PIEACK.bit.ACK9 = 1;

  // Insert ISR Code here

  // To receive more interrupts from this PIE group, acknowledge this interrupt
  // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

  // Next two lines for debug only to halt the processor here
  // Remove after inserting ISR Code
//  asm ("      ESTOP0");
//  for(;;);

}
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happy_10 发表于 2020-5-29 23:35 | 显示全部楼层
还有什么现象？
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 楼主| pengf 发表于 2020-5-29 23:36 | 显示全部楼层
现在发送应该是成功发送到总线上了，因为将断点设置在ECanbShadow.CANTA.bit.TA25 = 1;                      // Clear TA5
可以看到kk的值小于10000，小于10000表示发送成功，但是我查看CANES.TM 发现这个位的值一直为0，这意味着CAN模块没有发送数据。
这里感觉有点矛盾
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wenfen 发表于 2020-5-29 23:38 | 显示全部楼层
接受不到CAN设备发送过来的数据?
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 楼主| pengf 发表于 2020-5-29 23:39 | 显示全部楼层
嗯，因为while((ECanbRegs.CANRMP.all != 0x10000000 )&&(z<10000)) z++;
之后的z一直为10000意味着没有收到消息
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zwll 发表于 2020-5-29 23:42 | 显示全部楼层
上位机接收下位机应答数据帧时，需要对协议识别码做滤波屏蔽，否则会接收到下位机发送
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zhaoxqi 发表于 2020-5-29 23:44 | 显示全部楼层

你有什么打算呢？或者你想知道什么？
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 楼主| pengf 发表于 2020-5-29 23:45 | 显示全部楼层
否则会接收到下位机发送
的其它协议的数据帧，上位机通讯协议识别码为 ID 的高 12 位（识别码:0x102）。
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 楼主| pengf 发表于 2020-5-29 23:46 | 显示全部楼层
这个滤波屏蔽怎么设置呢？
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