不能进入中断

2万 · 2020-7-5 17:33

通过8个通道采集AD，定时器触发采样率为1个周期80个点，然后将通道ADC12CH_0和通道ADC12CH_1采集的数据存储在开辟的两段FRAM区域里面，用序列通道（ADC12CONSEQ_1）采。但是，不能进入中断。

2万 · 2020-7-5 17:36

楼主程序可以公开吗？贴程序看下吧，这么说看不出什么原因

2万 · 2020-7-5 17:40

用的MCU是MSP430FR5969

#include <msp430.h>

#define FRAM_TEST_START0 0x9000
#define FRAM_TEST_START1 0xD000

volatile unsigned long ADC_Data[8];
unsigned char count = 0;
unsigned long *FRAM_write_ptr;

void GPIOInit(void)
{

// Configure all un-used GPIO to lowest power state
P1DIR = 0xFF;
P1OUT = 0;

P1SEL1 |= BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5;// Configure P1.0 P1.1 P1.2 P1.3 P1.4 P1.5for ADC
P1SEL0 |= BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5;// A0~A5

P2DIR = 0xFF;
P2OUT = 0;
// P2OUT = 0xFF;
P2SEL1 |= BIT3 | BIT4; // Configure P2.3 and P2.4 for ADC
P2SEL0 |= BIT3 | BIT4; // A6~A7

P3DIR = 0xFF;
P3OUT = 0;
// P2OUT = 0xFF;

P4DIR = 0xFF;
P4OUT = 0;

PJOUT = 0;
PJSEL0 = BIT4 | BIT5;                // For XT1
PJDIR = 0xFFFF;

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
}

void clockInit(void)
{
// Clock System Setup
CSCTL0_H = CSKEY >> 8;                // Unlock CS registers
CSCTL1 = DCOFSEL_6;                   // Set DCO to 8MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; // Set ACLK = XT1; MCLK = SMCLK = DCO
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL4 &= ~LFXTOFF;                   // Enable LFXT1
do
{
      CSCTL5 &= ~LFXTOFFG;             // Clear XT1 fault flag
      SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG);             // Test oscillator fault flag
CSCTL0_H = 0;                         // Lock CS registers

}

void TimerInit(void)
{

// Configure Timer0_A
TA0CCR0 = 8-1;                         // 32K/32 = 1000Hz freq.
TA0CCTL1 = OUTMOD_7;                   // CCR1 reset/set
TA0CCR1 = 4;                            // 16/32 = 50% duty cycl
TA0CTL = TASSEL__ACLK | MC__UP | TACLR; // ACLK, up mode, clear TAR
}

void FRAMWrite(unsigned long data)
{

*FRAM_write_ptr++ = data;

}

void ADC12Init()
{
// By default, REFMSTR=1 => REFCTL 是配置内部参考电压的寄存器
// while(REFCTL0 & REFGENBUSY);                            // 如果参考电压发生器busy, 等待
// REFCTL0 |= REFVSEL_2 | REFON;                         // 选择内部参考源 ref = 2.5V，使能内部参考源

// Configure ADC12
ADC12CTL0 = ADC12SHT0_2 | ADC12ON | ADC12MSC;    // Sampling time, S&H=16, ADC12 on
ADC12CTL1 = ADC12SHP + ADC12SHS_1 + ADC12SSEL_1 + ADC12CONSEQ_1;    // Use sampling timer, Use TA0CCR1 output as trigger , sequence channel
ADC12CTL2 |= ADC12RES_2 + ADC12PWRMD; // 12-bit conversion results, low power mode       ADC12CTL3 = ADC12CSTARTADD_0;// | ADC12CSTARTADD_1;

// while(!(REFCTL0 & REFGENRDY));       // 等待参考源生效

ADC12IER0 |= ADC12IE0;                //开中断

ADC12MCTL7 |= ADC12INCH_7 | ADC12VRSEL_1;       // A2 ADC input select; Vref=AVCC
ADC12MCTL1 |= ADC12INCH_1 | ADC12VRSEL_1;
ADC12MCTL0 |= ADC12INCH_2 | ADC12VRSEL_1;
ADC12MCTL3 |= ADC12INCH_3 | ADC12VRSEL_1;
ADC12MCTL4 |= ADC12INCH_4 | ADC12VRSEL_1;
ADC12MCTL5 |= ADC12INCH_5 | ADC12VRSEL_1;
ADC12MCTL6 |= ADC12INCH_6 | ADC12VRSEL_1;
ADC12MCTL0 |= ADC12INCH_0 | ADC12VRSEL_1 + ADC12EOS;

ADC12CTL0 |= ADC12ENC | ADC12SC; //转换使能，开始转换
}

int main(void)
{
WDTCTL = WDTPW | WDTHOLD;                // Stop WDT
GPIOInit();
clockInit();
TimerInit();
ADC12Init();

while (1)
{
      __bis_SR_register(LPM3_bits | GIE); // LPM3, ADC12_ISR will force exit
      __no_operation();                // For debugger
}

}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
{
      case ADC12IV_NONE:       break; // Vector  0:  No interrupt
      case ADC12IV_ADC12OVIFG:  break; // Vector  2:  ADC12MEMx Overflow
      case ADC12IV_ADC12TOVIFG: break; // Vector  4:  Conversion time overflow
      case ADC12IV_ADC12HIIFG:  break; // Vector  6:  ADC12BHI
      case ADC12IV_ADC12LOIFG:  break; // Vector  8:  ADC12BLO
      case ADC12IV_ADC12INIFG:  break; // Vector 10:  ADC12BIN
      case ADC12IV_ADC12IFG0:          // Vector 12:  ADC12MEM0 Interrupt

         ADC_Data[0] = ADC12MEM0;
         ADC_Data[1] = ADC12MEM1;

         FRAM_write_ptr = (unsigned long *)FRAM_TEST_START0;
         FRAMWrite(ADC_Data[0]);                         // Endless loop
         ADC12MCTL0&=~ADC12INCH_2; //通道清2

         FRAM_write_ptr = (unsigned long *)FRAM_TEST_START1;
         FRAMWrite(ADC_Data[1]);                         // Endless loop
         ADC12MCTL1&=~ADC12INCH_3; //通道清3

            // Exit from LPM0 and continue executing main
            __bic_SR_register_on_exit(LPM3_bits);
         break;
      case ADC12IV_ADC12IFG1: break; // Vector 14:  ADC12MEM1
      case ADC12IV_ADC12IFG2: break; // Vector 16:  ADC12MEM2
      case ADC12IV_ADC12IFG3: break; // Vector 18:  ADC12MEM3
      case ADC12IV_ADC12IFG4: break; // Vector 20:  ADC12MEM4
      case ADC12IV_ADC12IFG5: break; // Vector 22:  ADC12MEM5
      case ADC12IV_ADC12IFG6: break; // Vector 24:  ADC12MEM6
      case ADC12IV_ADC12IFG7: break; // Vector 26:  ADC12MEM7
      case ADC12IV_ADC12IFG8: break; // Vector 28:  ADC12MEM8
      case ADC12IV_ADC12IFG9: break; // Vector 30:  ADC12MEM9
      case ADC12IV_ADC12IFG10:  break; // Vector 32:  ADC12MEM10
      case ADC12IV_ADC12IFG11:  break; // Vector 34:  ADC12MEM11
      case ADC12IV_ADC12IFG12:  break; // Vector 36:  ADC12MEM12
      case ADC12IV_ADC12IFG13:  break; // Vector 38:  ADC12MEM13
      case ADC12IV_ADC12IFG14:  break; // Vector 40:  ADC12MEM14
      case ADC12IV_ADC12IFG15:  break; // Vector 42:  ADC12MEM15
      case ADC12IV_ADC12IFG16:  break; // Vector 44:  ADC12MEM16
      case ADC12IV_ADC12IFG17:  break; // Vector 46:  ADC12MEM17
      case ADC12IV_ADC12IFG18:  break; // Vector 48:  ADC12MEM18
      case ADC12IV_ADC12IFG19:  break; // Vector 50:  ADC12MEM19
      case ADC12IV_ADC12IFG20:  break; // Vector 52:  ADC12MEM20
      case ADC12IV_ADC12IFG21:  break; // Vector 54:  ADC12MEM21
      case ADC12IV_ADC12IFG22:  break; // Vector 56:  ADC12MEM22
      case ADC12IV_ADC12IFG23:  break; // Vector 58:  ADC12MEM23
      case ADC12IV_ADC12IFG24:  break; // Vector 60:  ADC12MEM24
      case ADC12IV_ADC12IFG25:  break; // Vector 62:  ADC12MEM25
      case ADC12IV_ADC12IFG26:  break; // Vector 64:  ADC12MEM26
      case ADC12IV_ADC12IFG27:  break; // Vector 66:  ADC12MEM27
      case ADC12IV_ADC12IFG28:  break; // Vector 68:  ADC12MEM28
      case ADC12IV_ADC12IFG29:  break; // Vector 70:  ADC12MEM29
      case ADC12IV_ADC12IFG30:  break; // Vector 72:  ADC12MEM30
      case ADC12IV_ADC12IFG31:  break; // Vector 74:  ADC12MEM31
      case ADC12IV_ADC12RDYIFG: break; // Vector 76:  ADC12RDY
      default: break;
}
}