TI 公司的TPS3860x0系列是四路电压监视器,具有可编程延迟(1.4ms到10s)和看门狗定时器, 监视电压大于0.4V,阈值精度0.25%,非常低的静态电流(12uA),主要用在模拟加序,所有的DSP和MCU应用, 所有的FPGA/ASIC应用.本文介绍了TPS3860x0系列主要特性,方框图, 典型应用电路,以及TPS386000 和TPS386040的评估模块主要特性,电路图和所用材料清单.
Quad Supply Voltage Supervisors with Programmable Delay and Watchdog Timer
The TPS3860x0 family of voltage supervisors can monitor four power rails that are greater than 0.4V with a 0.25% (typical) threshold accuracy. Each of the four supervisory circuits (SVS-n) assert a RESETn or RESETn output signal when the SENSEm input voltage drops below the programmed threshold. With external resistors, the threshold of each SVS-n can be programmed (where n = 1, 2, 3, 4 and m = 1, 2, 3, 4L, 4H).
Each SVS-n has a programmable delay before releasing RESETn or RESETn, and the delay time can be set from 1.4ms to 10s through the CTn pin connection. Only SVS-1 has an active-low manual reset (MR) input; a logic-low input to MR asserts RESET1 or RESET1.
SVS-4 monitors the threshold window using two comparators. The extra comparator can be configured as a fifth SVS to monitor negative voltage with voltage reference output VREF.
The TPS3860x0 has a very low quiescent current of 12&mciro;A (typical) and is available in a small, 4mm x 4mm, QFN-20 package.
TPS3860x0主要特性:
4 Complete SVS Modules on 1 Silicon Platform
Programmable Delay Time: 1.4ms to 10s
Very Low Quiescent Current: 12µA typ
Threshold Accuracy: 0.25% typ
Adjustable Threshold Down to 0.4V
SVS-1: Manual Reset (MR) Input
SVS-4: Window Comparator or Low-Voltage Sensing with VREF (1.2V) Pin
Watchdog Timer with Dedicated Output
Well-Controlled RESETn Output During Power-Up
TPS386000: Open-Drain RESETn and WDO
TPS386020: Open-Drain RESETn and WDO
TPS386040: Push-Pull RESETn and WDO
TPS386060: Push-Pull RESETn and WDO
Package: 4mm x 4mm, 20-pin QFN
TPS3860x0应用:
Analog Sequencing
All DSP and Microcontroller Applications
All FPGA/ASIC Applications
图1.TPS386000 方框图
图2.TPS386020 方框图
图3.TPS386040 方框图
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