InitPll(DSP28_PLLCR,DSP28_CLKINDIV); 定时器配置的DSP28_PLLCR=5，DSP28_CLKINDIV=0（就是说使能2分频）外部晶振是20MHz，所以SYSCLK是50MHz。中断函数如下：
interrupt void cpu_timer0_isr(void){
CpuTimer0.InterruptCount++;
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1;
GpioDataRegs.GPATOGGLE.bit.GPIO8 = 1;
EDIS;
StopCpuTimer0();
DISABLE_TIMER1_INT;
ConfigCpuTimer(&CpuTimer0, 50, 1000000);
StartCpuTimer0();
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
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