I stumbled upon this page which brought up some questions:
https://developer.arm.com/too...
The obsfucated RTL is synthesizable and should be cycle accurate. I don\'t see any technical reasons why the RTL could not be verilated and run as a simulator. I understand that you would need to add peripherals to the buses to make it useful along with some glue to handle JTAG. Am I missing something or has no one gone down that path?
On the licensing front I know I agreed to a click-thru license to download the designstart package but I can\'t seem to locate it. Does anyone have a link or know what the distribution restrictions of a verilated binary produced from the obsfucated RTL are?
Bonus question: Does anyone have a rough estimate of the frequency that the ARM cycle model can run at on a modern PC? 10kHz? 100kHz? 1MHz? |
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楼主
