why can\'t MMU observe the table entry change made by its company core ?
working for Cortex-A55MP, EL1 in Aarch32, svc mode:
Both 2 level of table entry are attributed as (inner WB/WA, and outer WB/WA) and
the MMU is set TTBR0 as (N=0, Inner WB WA , and Outer WB WA),
is this not enough to have MMU to observe the page table entry change made by the same CPU core ?
If we add a DCCMVAC after modification of page entry, it works. Why ? |
楼主
标题置顶
标题高亮
