I couldnt find any examples as such, as far as I\'ve seen, the two data in the busses HWDATA and HRDATA are never used at the same time as other. Is there any scenario where in one time cycle, the HWDATA holds the data of the current transfer while HRDATA holds the data of the previous transfer.
Also, I need to add/encorporate AHB interface to a processor with Load/Store Architecture that has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate data bus port must be present? |
|
楼主
