Hi. I recently got the ARM AMBA specification in my work, and now I am learning stuffs. But the Additional control information got me stuck for a day haha
My questions are
What is the reason to use the Cacheable bit in the Cache support? I wish I could get the example In real industry standard.When reading the speicfication on the Cacheable bit, they say the multiple write can merge together in multiple writes. I cannot catch the viivd picture on this situation. Does this mean the several master can write the data on cache? can i get some real life example so that I can visualize the real problem with this write section?I want to check whether I understand right in read section. So if the read happens with the cacheable bit flag HIGH, it means the data which the Master wants to read from the memory could be cached in the cache nearby the Master. And the principle of the Cache getting the data nearby the address which the Master asks to the Slave get applied here so some are \'pre-fetched\' in the Cache. Is this right to understand what the specification explains??What I feel while writing this question is that all understanding I have right now is all wrong. I feel like I got a wrong start move from the beginning. |
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