在开发板上验证DDR3,用Coregen,生成DDR MIG,MAP的时候出现下面的错误:
ERROR:Place:1333 - Following IOB's that have input/output programming are locked
to the bank 1 that does not support such values
IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
BIDIR, DRIVE_STR = NR
List of locked IOB's:
mcb4_dram_udqs_n
mcb4_dram_udqs
mcb4_dram_dqs_n
mcb4_dram_dqs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
有几个问题请教下:
1、已经指定了DDR3在Bank4上,为什么“are locked to the bank 1”?
2、这都是按照MIG_Design的教程操作的,出现这样的错误,是不是说明软件有Bug?
3、我在网上查了,也有很多在设计DDR2的时候出现这样的问题,但没有具体的解答方法 |