请教综合实现中出现的问题,请诸位出手.
出错信息如下:FATAL_ERROR:Par:pwr_task.c:66:1.2 - Unhandled Xdm exception Process will terminate.
好像是布局布线通不过.详细信息如下:
Phase 3 : 47 unrouted;
(Par is working to improve performance) REAL time: 20 secs
Phase 4 : 55 unrouted;
(Par is working to improve performance) REAL time: 21 secs
Phase 5 : 0 unrouted;
Updating file: Top_Module.ncd with current fully routed design.
EXCEPTION:Xdm:ModelImp.c:794:$Id: ModelImp.c,v 1.28 2009/06/12 19:55:28 jdl Exp $ - Xdm_Exception::CannotWriteFile
file='Top_Module.ncd'
For technical support on this
issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
WARNING:ProjectMgmt - File F:/FH1605FPGA51/Top_Module.ncd is missing.
WARNING:ProjectMgmt - File F:/FH1605FPGA51/Top_Module_par.xrpt is missing. |
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