查获的资料
By placing the PERIOD constraint on the input clock, the Xilinx tools automatically:
• Derive a new PERIOD constraint for each of the DLL/DCM/PLL output clocks
• Determine the clock relationships between the output clock domains, and
automatically perform an analysis for any paths between these clock domains.
嘻嘻，
1，offset out 的参考时序是pad端输入时钟这个明白否？
2，比如说，约束的值是10ns，这个10ns是相对于clk_in（pad），如果clk_in经DCM延时了4ns，变成了clk_dcm，输出的数据是以clk_dcm时钟的沿打出的，那么布局布线时数据输出延时就是6ns，软件自动算上了DCM的延时4ns。明白了吧！
楼主
