void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
u32 tmp = 0,/* pllmull = 0, pllsource = 0,*/ presc = 0;
u32 pll1mull = 0, pll1source = 0, prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & CFGR_SWS_Mask;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
RCC_Clocks->SYSCLK_Frequency = HSI_Value;
break;
case 0x04: /* HSE used as system clock */
RCC_Clocks->SYSCLK_Frequency = HSE_Value;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
pllmull = ( pllmull >> 18) + 2;
pllsource = RCC->CFGR & CFGR_PLLSRC_Mask
if (pllsource == 0x00)
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
}
else
{/* HSE selected as PLL clock entry */
if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
{/* HSE oscillator clock divided by 2 */
RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
}
else
{
RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
}
}
break;
/* STM32 connectivity line devices */
/* Get PLL1 clock source and multiplication factor */
pll1mull = RCC->CFGR & CFGR_PLL1Mull_Mask;
pll1mull = ( pll1mull >> 18) + 2; /* !!!!!!!!!!! case where mul = 6.5 !!!!!!!!!!!!!!! */
pll1source = RCC->CFGR & CFGR_PLL1SRC_Mask;
if (pll1source == 0x00)
{/* HSI oscillator clock divided by 2 selected as PLL1 clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pll1mull;
}
else
{/* PREDIV1 selected as PLL1 clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
if (prediv1source == 0)
{/* HSE oscillator clock selected as PREDIV1 clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pll1mull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pll1mull;
}
}
break;
default:
RCC_Clocks->SYSCLK_Frequency = HSI_Value;
break;
}
/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
/* Get HCLK prescaler */
tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
tmp = tmp >> 4;
presc = APBAHBPrescTable[tmp];
/* HCLK clock frequency */
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
/* Get PCLK1 prescaler */
tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
tmp = tmp >> 8;
presc = APBAHBPrescTable[tmp];
/* PCLK1 clock frequency */
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
/* Get PCLK2 prescaler */
tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
tmp = tmp >> 11;
presc = APBAHBPrescTable[tmp];
/* PCLK2 clock frequency */
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
/* Get ADCCLK prescaler */
tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
tmp = tmp >> 14;
presc = ADCPrescTable[tmp];
/* ADCCLK clock frequency */
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
} |
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