void initClock()
{
UCSCTL6 &= ~XT1OFF; //启动XT1
P5SEL |= BIT2 + BIT3; //XT2引脚功能选择
UCSCTL6 &= ~XT2OFF; //打开XT2
// PMMCTL0 |=PMMPW+ PMMCOREV_3;
PMMCTL0_H = 0xA5; //开PMM电源管理
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //配置SVML电压
PMMCTL0 = PMMPW + PMMCOREV_2; //配置内核电压
while((PMMIFG & SVSMLDLYIFG ) == 0); //等待设置完成
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //判断内核电压是否上升到VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //如果没有等待
SVSMLCTL &= ~SVMLE; //关掉SVML模块
PMMCTL0_H = 0X00; //锁存配置
__bis_SR_register(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4; //选择DCO频率区域
UCSCTL1 = DCORSEL_5; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_4 + 2; //D=16，N=1 16*2*（4/8)=16
UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8,FLLREFCLK时钟源为XT2CLK；DCOCLK=D*(N+1)*(FLLREFCLK/n);DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK的时钟源为DCOCLKDIV,MCLK\SMCLK的时钟源为DCOCLK
UCSCTL5 = DIVA_5 +DIVS_1; //ACLK由DCOCLKDIV的32分频得到，SMCLK由DCOCLK的2分频得到
//最终MCLK:24MHZ,SMCLK:12MHZ,ACLK:48KHZ
__bic_SR_register(SCG0); //Enable the FLL control loop
}
void initClock()
{
UCSCTL6 &= ~XT1OFF; //启动XT1
P5SEL |= BIT2 + BIT3; //XT2引脚功能选择
UCSCTL6 &= ~XT2OFF; //打开XT2
// PMMCTL0 |=PMMPW+ PMMCOREV_3;
PMMCTL0_H = 0xA5; //开PMM电源管理
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //配置SVML电压
PMMCTL0 = PMMPW + PMMCOREV_2; //配置内核电压
while((PMMIFG & SVSMLDLYIFG ) == 0); //等待设置完成
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //判断内核电压是否上升到VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //如果没有等待
SVSMLCTL &= ~SVMLE; //关掉SVML模块
PMMCTL0_H = 0X00; //锁存配置
__bis_SR_register(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4; //选择DCO频率区域
UCSCTL1 = DCORSEL_4; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_4 +1; //D=16，N=1 16*2*（4/8)=16
UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8,FLLREFCLK时钟源为XT2CLK；DCOCLK=D*(N+1)*(FLLREFCLK/n);DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK的时钟源为DCOCLKDIV,MCLK\SMCLK的时钟源为DCOCLK
UCSCTL5 = DIVA_5 +DIVS_1; //ACLK由DCOCLKDIV的32分频得到，SMCLK由DCOCLK的2分频得到
//最终MCLK:16MHZ,SMCLK:8MHZ,ACLK:32KHZ
__bic_SR_register(SCG0); //Enable the FLL control loop
}
void initClock()
{
UCSCTL6 &= ~XT1OFF; //启动XT1
P5SEL |= BIT2 + BIT3; //XT2引脚功能选择
UCSCTL6 &= ~XT2OFF; //打开XT2
PMMCTL0_H = 0xA5; //开PMM电源管理
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //配置SVML电压
PMMCTL0 = PMMPW + PMMCOREV_2; //配置内核电压
while((PMMIFG & SVSMLDLYIFG ) == 0); //等待设置完成
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //判断内核电压是否上升到VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //如果没有等待
SVSMLCTL &= ~SVMLE; //关掉SVML模块
PMMCTL0_H = 0X00; //锁存配置
__bis_SR_register(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4;
UCSCTL1 = DCORSEL_4; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_4 + 1; //D=16，N=1
UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8,FLLREFCLK时钟源为XT2CLK；DCOCLK=D*(N+1)*(FLLREFCLK/n);DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK的时钟源为DCOCLKDIV,MCLK\SMCLK的时钟源为DCOCLK
UCSCTL5 = DIVA_5 +DIVS_4; //ACLK由DCOCLKDIV的32分频得到，SMCLK由DCOCLK的2分频得到
//最终MCLK:16MHZ,SMCLK:1MHZ,ACLK:32KHZ
__bic_SR_register(SCG0); //Enable the FLL control loop
} |
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