fpga减法运算

只看该作者 · 2020-12-7 10:57

fpga做减法的时候，比如两个8位数相减。在程序里面，写减法的时候。
需要对输入数据进行最高位扩展。最后的结果是一个9bit数据。

module sub8(a,b,c,clk);



input [7:0] a,b;

output[8:0] c;

input clk;



reg [8:0] c;

always [url=home.php?mod=space&uid=72445]@[/url] ( posedge clk) begin

//c <= a - b;

c <= {a[7], a} - {b[7],b};

end



endmodule



测试模块



module sub8_tb;



reg [7:0] a,b;

wire[8:0] c;

reg clk;



initial begin

clk = 0;

a = 8'd100;

b = 8'd17;



#15 ;

a = 8'd100;

b = -8'd17;



#15 ;

a = -8'd100;

b = 8'd17;



#15 ;

a = -8'd100;

b = -8'd17;



// test overflow

#15;

a = 8'd100; // res should be 132.

b = -8'd32;



#15;

a = -8'd100; // res should be -132.

b = 8'd32;



#20;

$stop;

end

sub8 m0(a,b,c,clk);

always #5 clk = ~clk;



endmodule